VLSI Frontend CAD Applications Engineer

North American Production Sharing, Inc.; Tijuana; Presencial; MXN 600.000 - 1.200.000; Jornada completa

Descripción de la vacante

North American Production Sharing, Inc. in Mexico is seeking a CAD-focused engineer to advance Synthesis, Place and Route, and Formal Verification for diverse mobile, compute, AI, and IoT SoCs.

You will help define tools and methodologies, collaborate with Implementation and Physical Design teams, and interface with EDA vendors. Ideal candidates hold a Master’s or PhD in EE/CE and have 2–6 years in VLSI CAD, including Synthesis and Place & Route, plus 2–6 years of Python/TCL scripting.

Formación

• Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field.
• 2–6 years of experience in VLSI CAD, preferably Synthesis, Floorplan, Place and Route on SoCs.
• 2–6 years of experience with scripting languages: Python and TCL.

Responsabilidades

• Participate in the Synthesis, Place and Route and Formal verification flows enablement for foundry advanced process nodes.
• Participate to the tuning of design recipes to address area and turn-around time on subsystems like Modem, GPU, CPU, DDR, Camera, Video, NSP.
• Interface with EDA vendor Application Engineers to resolve block convergence problems for design teams.
• Help specify new CAD solutions addressing PPA requirements for the design teams.
• Deep dive on implementation issues such as cell legalization, congestion hotspots, clock tree and CTS.

Conocimientos

Synthesis

Place and Route

Formal Verification

CAD methodologies

Block-level/SoC CAD

Scripting languages

Educación

Master's degree or PhD in Computer Engineering, Electrical Engineering, or related field

Herramientas

Python

TCL

Descripción del empleo

The position requires Synthesis or/and Place and Route experience and CAD development skills to define and develop implementation tools and methodologies for PPA, Quality and shortening design cycle time, in close collaboration with Implementation and Physical Design teams.

This role’s responsibilities will include.

• Improving the SoC Synthesis, Formal Verification, Place and Route methodologies for diverse Mobile, Compute, AI, IoT chips.
• Enabling new features from EDA tools or/and internal tools for PPA, turn-around time or enabling new advanced process nodes.
• Support design teams on CAD solutions, analyze their requests, and address their requests through ticket queues.
• Interfacing with EDA vendors to enable production-ready tool sets that satisfy project’s requirement.
• Setting up, augmenting, and maintaining a regression of complex Synthesis, P&R designs.
• Innovating on tool/flow techniques for area reduction, dynamic power reduction and turn-around time, leading to participation to patents.

Preferred Qualifications.

• Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field.
• 2-6 years of experience in VLSI CAD, preferably Synthesis, Floorplan, Place and Route on SoCs at either top-level or block-level.
• 2-6 years of experience with scripting tools and programming languages: Python and TCL preferred.

Principal Duties and Responsibilities.

• Participate to the Synthesis, Place and Route and Formal verification flows enablement for foundry advanced process nodes.
• Participate to the tuning of design recipes to address specific objectives such as area, turn-around time on various subsystems such as Modem, GPU, CPU, DDR, Camera, Video, NSP.
• Interface and drive EDA vendor Application Engineers on the resolution of block convergence problems faced by the design teams.
• Participate to the specification of new CAD solutions addressing the PPA requirements of the design teams.
• Deep dive on Implementation issues, such as cell legalization issues, congestion hotspots, always-on feedthrough management, clock H-tree and CTS etc.
• Participate along with talented AI team to R&D initiatives driving differentiation in terms of die area reduction and turn-around time.