SoC Verification Engineer – Pre & Post-Silicon

Qualcomm

Tijuana

Presencial

MXN 450.000 - 750.000

Jornada completa

14 días+

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Descripción de la vacante

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA in Tijuana seeks motivated Engineer and Senior Engineer candidates to join our Pre‑Silicon and Post‑Silicon SoC Verification team, verifying next‑generation SoCs powering mobile AI and HPC products.

You will work across pre‑silicon simulation, emulation, acceleration, and post‑silicon bring‑up, collaborating with cross‑functional teams, driving verification closure, and mentoring colleagues while advancing reusable components and

Formación

Bachelor’s or Master’s degree in electrical engineering, computer engineering, computer science, or related field.
Engineer: typically 2+ years of relevant design verification, validation, or SoC debug experience.
Sr. Engineer: typically 4+ years of relevant experience with demonstrated ownership of complex verification, validation, or silicon bring‑up deliverables.
Strong knowledge of System Verilog, UVM, C/C++, assertion‑based verification, coverage‑driven verification, and system‑level use‑case verification.
Experience developing or using verification environments from architecture/specification through signoff, including regression, coverage, and debug flows.
Understanding of post‑silicon validation concepts such as bring‑up, ATE/vector debug, silicon failure triage, hardware/software interaction, or correlation with pre‑silicon results.
Strong understanding of computer architecture, digital design fundamentals, and SoC integration concepts.
Excellent communication, collaboration, ownership, and problem‑solving skills.

Responsabilidades

Develop and execute verification plans for SoC, subsystem, and IP‑level features across pre‑silicon and post‑silicon phases.
Build, enhance, and maintain SystemVerilog/UVM, C/C++, processor‑based, emulation, and acceleration verification environments.
Create directed, constrained‑random, stress, performance, power, and system‑level test scenarios to validate architecture and real‑use‑case behavior.
Develop assertions, functional coverage models, checkers, scoreboards, and signoff metrics for verification closure.
Debug RTL, testbench, emulation, firmware, ATE/vector, and silicon bring‑up issues using logs, waveforms, traces, and hardware debug data.
Support post‑silicon validation, silicon characterization, ATE pattern debug, failure triage, and correlation between simulation, emulation, and silicon results.
Drive coverage closure, regression health, bug tracking, and verification signoff using functional, code, assertion, and scenario coverage metrics.
Participate in architecture, micro‑architecture, design, validation, and test‑plan reviews to ensure verification and bring‑up requirements are captured early.
Verify complex SoC features including multi‑core CPU systems, cache coherency and interconnect fabrics, DDR/HBM memory subsystems, PCIe/CXL/Ethernet/high‑speed interfaces, security, performance, and power‑management features.
For Engineer level: execute assigned verification tasks, develop tests and checkers, debug failures, maintain regressions, and contribute to coverage and bring‑up activities.
For Senior Engineer level: own feature/subsystem verification from plan to closure, lead debug across teams, mentor engineers, identify schedule and quality risks, and drive methodology/automation improvements.
Contribute to reusable verification components, scripting automation, AI‑assisted verification workflows, and continuous improvement of pre‑silicon and post‑silicon validation processes.