Senior Analog/Mixed-Signal Layout Engineer

Ciena; México; Presencial; MXN 900.000 - 1.300.000; Jornada completa

Descripción de la vacante

Ciena is seeking an Analog Layout Engineer in Mexico to contribute to high-speed analog circuit layouts using deep-submicron CMOS technologies, including FinFETs. You will collaborate with senior designers to plan, place, route, and verify layouts, ensuring device performance and layout quality.

Responsibilities include evaluating layout feasibility, performing verification checks, and driving productivity with tool features while working with cross-functional teams.

Formación

• Education: Bachelor's degree in Electrical Engineering or a related field.
• Experience: 5+ years of relevant industry experience.
• Custom analog and mixed-signal layout design using deep-submicron CMOS devices, including FinFET transistors.
• Collaboration within an existing team environment and application of a constructive approach to team activities.
• Communication and interpersonal skills applied in collaboration with cross-functional teams.
• Custom layout design of analog and mixed-signal designs, including ADC, DAC, PLL, and SERDES.
• Utilization of industry-standard layout tools, including Cadence Virtuoso, Siemens Calibre, and Ansys Totem, and application of layout design flows for advanced technology nodes.

Responsabilidades

• Evaluate layout feasibility for circuit designs in collaboration with senior analog designers, considering design trade-offs and team input.
• Create layouts for assigned analog blocks through floor planning, placement, and routing.
• Perform DRC, ANT, LVS, PERC, EM, and IR verification checks to confirm layout quality.
• Investigate layout tool and process features that can enhance productivity.
• Provide regular status updates, participate in team meetings, and share knowledge with the group.

Conocimientos

Analog layout

Mixed-signal layout

FinFET CMOS

Team collaboration

Communication

Layout verification

ADC DAC PLL SERDES

Educación

Bachelor's degree in Electrical Engineering

Herramientas

Cadence Virtuoso

Siemens Calibre

Ansys Totem

Descripción del empleo

Ciena is seeking an Analog Layout Engineer in Mexico to contribute to high-speed analog circuit layouts using deep-submicron CMOS technologies, including FinFETs. You will collaborate with senior designers to plan, place, route, and verify layouts, ensuring device performance and layout quality.

Responsibilities include evaluating layout feasibility, performing verification checks, and driving productivity with tool features while working with cross-functional teams.