Entry-Level Mask Layout Designer for Analog IP

North American Production Sharing, Inc.; Tijuana; Sur place; MXN 180 000 - 280 000; Plein temps

Avantages offerts par ce poste

Relocation bonus

Résumé du poste

North American Production Sharing, Inc. is seeking entry-level Mask Layout Designers to join an international team. No prior industry experience required—just strong academic knowledge and a passion for innovation.

You will develop block-level layouts for advanced node IP designs used in smartphones and wireless devices. You will use Cadence VXL and Calibre, collaborate with teams in the U.S., Ireland, and India, and contribute to design verification and layout efficiency while expanding your

Qualifications

• Associate’s degree or certificate in Computer Science, Mathematics, Electrical Engineering, or related field.
• Advanced English proficiency.
• Valid U.S. Visa; SENTRI or Global (Preferred).

Responsabilités

• Develop block-level layouts for advanced node mixed-signal IP designs used in smartphones and wireless devices.
• Create, verify, and revise IP designs applying analog layout principles: device matching, parasitic minimization, isolation techniques, and latch-up prevention.
• Utilize Cadence VXL and Calibre verification tools.
• Maintain layout databases using Design Management software.
• Collaborate with engineering teams across multiple global locations (U.S., Ireland, India).
• Report design status accurately and track schedules.
• Solve design and PDK issues proactively and communicate solutions clearly.
• Work effectively as part of an international team and continuously expand your skillset.

Connaissances

Advanced English

Team collaboration

Formation

Associate degree or certificate in CS/Math/EE

Bachelor’s degree in CS/Engineering

Outils

Cadence VXL

Calibre

Description du poste

North American Production Sharing, Inc. is seeking entry-level Mask Layout Designers to join an international team. No prior industry experience required—just strong academic knowledge and a passion for innovation.

You will develop block-level layouts for advanced node IP designs used in smartphones and wireless devices. You will use Cadence VXL and Calibre, collaborate with teams in the U.S., Ireland, and India, and contribute to design verification and layout efficiency while expanding your