Innovative Standard Cell Layout Engineer

Qualcomm; Tijuana; Presencial; MXN 420.000 - 720.000; Jornada completa

Descripción de la vacante

Qualcomm seeks a layout engineer to design and develop physical layouts for logic standard cells using Cadence Virtuoso, with SKILL and Python for automation. You will collaborate with circuit designers to ensure layouts meet performance and reliability requirements, and perform comprehensive layout verification.

Responsibilities include DRC/LVS/ERC checks, managing layout databases, and clear communication of design status within a globally distributed team including the US, Taiwan, and India.

Formación

• Associate degree or technical certificate in CS, Math, EE or related field.
• Foundational CMOS/IC design knowledge.
• Strong attention to detail and ability to work in a collaborative team.

Responsabilidades

• Design and develop physical layouts for logic standard cells using CAD tools like Cadence Virtuoso.
• Perform DRC, LVS, and ERC checks for layout verification.
• Collaborate with circuit designers to meet quality, performance, and reliability requirements.
• Maintain and manage layout databases and design data.
• Communicate design status and milestones with the engineering team.
• Identify and resolve design and PDK-related issues and document solutions.
• Coordinate with global teams (US, Taiwan, India) on layout tasks.

Conocimientos

Scripting & automation

Team collaboration

Attention to detail

Educación

Associate’s degree or technical certificate

Bachelor’s degree preferred

Herramientas

Cadence Virtuoso

Layout design tools

Descripción del empleo

Qualcomm seeks a layout engineer to design and develop physical layouts for logic standard cells using Cadence Virtuoso, with SKILL and Python for automation. You will collaborate with circuit designers to ensure layouts meet performance and reliability requirements, and perform comprehensive layout verification.

Responsibilities include DRC/LVS/ERC checks, managing layout databases, and clear communication of design status within a globally distributed team including the US, Taiwan, and India.