Analog IC Layout Engineer – Automotive Power & Mixed‑Signal

NXP Semiconductors NV; Guadalajara; On-site; MXN 350,000 - 700,000; Full time

Job summary

NXP Semiconductors is seeking an Analog IC Layout Engineer to join the Central Layout Group for the Power & Energy Business Line, focusing on Automotive Power Solutions. You will develop analog/mixed-signal layouts, support floorplanning, and drive layout optimization through tape-out while collaborating across global teams.

The role offers exposure to cross-functional engineering environments, DRC/LVS verification, and continuous improvement of layout methodologies in a multicultural setting.

Qualifications

• Bachelor or Master in Electrical Engineering, Electronics, Physics or Microelectronics.
• Experience with analog and mixed-signal IC layout.
• Knowledge of DRC/LVS concepts.
• Familiarity with Linux environments.
• Strong analytical and problem-solving abilities.

Responsibilities

• Develop analog and mixed-signal layout blocks from schematic to tape-out.
• Support floorplanning and physical implementation activities.
• Optimize layouts for performance, matching, reliability and manufacturability.
• Contribute to top-level integration activities.
• Participate in design reviews and sign-off activities.
• Collaborate with Analog Design, Verification, Package, Test and Product Engineering teams.

Skills

Analog IC Layout methodologies

Cadence Virtuoso Layout

DRC/LVS verification concepts

Linux working environment

Analytical and problem-solving skills

Multicultural collaboration

Fluent English

Education

Bachelor or Master Degree in Electrical Engineering, Electronics, Physics or Microelectronics

Tools

Cadence Virtuoso

Calibre

PVS

Job description

NXP Semiconductors is seeking an Analog IC Layout Engineer to join the Central Layout Group for the Power & Energy Business Line, focusing on Automotive Power Solutions. You will develop analog/mixed-signal layouts, support floorplanning, and drive layout optimization through tape-out while collaborating across global teams.

The role offers exposure to cross-functional engineering environments, DRC/LVS verification, and continuous improvement of layout methodologies in a multicultural setting.