Automotive Analog IC Layout Engineer

NXP Semiconductors; Región Centro; On-site; MXN 600,000 - 900,000; Full time

Job summary

NXP Semiconductors, located in the Central Layout Group, seeks an Analog IC Layout Engineer to contribute to analog/mixed-signal ICs for automotive power solutions. You will translate schematics to tape-out, support floorplanning, and optimize layouts for performance, reliability and manufacturability in a multicultural, international team.

Responsibilities include DRC/LVS/ERC verification, parasitic extraction, design reviews, and ensuring high-quality layout deliveries per NXP methodologies.

Qualifications

• Bachelor or Master degree relevant to IC design.
• Knowledge of analog layout methodologies.
• Fluent English communication in multicultural teams.

Responsibilities

• Develop Analog and Mixed-Signal layout blocks from schematic to tape-out.
• Support floorplanning and physical implementation activities.
• Optimize layouts for performance, matching, reliability and manufacturability.
• Contribute to top-level integration activities.
• Execute DRC, LVS, ERC and physical verification activities.
• Support parasitic extraction and post-layout analysis.
• Participate in design reviews and sign-off activities.
• Ensure high-quality layout deliveries following NXP methodologies.
• Collaborate with Analog Design, Verification, Package, Test and Product Engineering teams.
• Support troubleshooting and problem-solving activities during product development.
• Contribute to continuous improvement of layout methodologies and best practices.

Skills

Analog IC Layout

Linux

English communication

Team collaboration

Education

Bachelor or Master Degree in Electrical Engineering, Electronics, Physics or Microelectronics

Tools

Cadence Virtuoso Layout environment

Calibre

PVS

Job description

NXP Semiconductors, located in the Central Layout Group, seeks an Analog IC Layout Engineer to contribute to analog/mixed-signal ICs for automotive power solutions. You will translate schematics to tape-out, support floorplanning, and optimize layouts for performance, reliability and manufacturability in a multicultural, international team.

Responsibilities include DRC/LVS/ERC verification, parasitic extraction, design reviews, and ensuring high-quality layout deliveries per NXP methodologies.