Staff Physical Design Engineer: Mixed-Signal ASIC Innovator

Renesas Electronics Corp.; Sicilia; On-site; EUR 44,000 - 59,000; Full time

Benefits offered by this job

Bonus

Job summary

Renesas Electronics Corp. is seeking a Physical Design Engineer to join the Analog Backend team and drive digital island implementations within analog chips.

This role focuses on solving complex physical design challenges in mixed-signal environments, enabling robust, high-performance ASICs. You will implement core physical design tasks, optimize for performance and reliability, and perform chip-level power integrity analyses across multiple voltage domains.

Qualifications

• Experience in ASIC Physical Design.
• Knowledge of floorplanning, placement, CTS, routing, and sign-off checks.
• Knowledge of power integrity analysis (IR drop and electromigration).
• A team player who enjoys working in an international, collaborative environment.
• Analog Layout experience is a plus.

Responsibilities

• Implement key aspects of the ASIC physical design flow, including floorplanning, placement optimization, clock tree synthesis, routing, and physical verification.
• Optimize designs for performance, reliability, and manufacturability.
• Perform chip-level power integrity analysis across multiple voltage domains (IR drop, signal EM, and power EM).
• Work on digital implementation embedded in analog environments.
• Collaborate with global cross-functional teams including analog designers and verification engineers.

Skills

ASIC Physical Design

Floorplanning

Placement

CTS

Routing

Sign-off checks

Power integrity

IR drop

Electromigration

Analog Layout

Collaboration

Job description

Renesas Electronics Corp. is seeking a Physical Design Engineer to join the Analog Backend team and drive digital island implementations within analog chips.

This role focuses on solving complex physical design challenges in mixed-signal environments, enabling robust, high-performance ASICs. You will implement core physical design tasks, optimize for performance and reliability, and perform chip-level power integrity analyses across multiple voltage domains.