Senior SoC Functional Verification Architect

OPENCHIP & SOFTWARE TECHNOLOGIES; Roma; Hybrid; EUR 120,000 - 180,000; Full time

Benefits offered by this job

Hybrid work environment

Flexible schedule

Remuneration aligned with experience

Job summary

Openchip & Software Technologies S.L. in Rome seeks a Functional Verification Principal Engineer to drive verification across architecture, design and software teams. You will develop high-level models, UVM environments, and HW/SW co-debug capabilities to ensure top performance of complex SoC/IP.

You will mentor teams, coordinate verification activities, and deliver robust verification across emulation and simulation platforms, with strong SystemVerilog, SystemC/C++, and formal techniques.

Qualifications

• Master degree in a relevant field is required.
• Minimum 15 years of verification experience in complex SoC or IP.
• Strong knowledge of SystemVerilog/UVM and SystemC/C++.
• Experience with constrained random and functional coverage.
• Familiarity with formal verification and UPF.
• HW-SW co-verification, simulation and debug skills.
• Scripting languages (Bash/Perl/Python) desirable.

Responsibilities

• Reading and analysing system and architecture requirements and documents.
• Developing detailed test and coverage plans based on architecture.
• Developing verification methodologies for scalable, portable environments.
• Building and maintaining verification environments in SystemVerilog/UVM/SystemC/C++, including stimulus, checkers, assertions, trackers, and coverage.
• Executing verification plans, including design bring-up, regression, and debug of failures.
• Using verification tools, CI, bug tracking, and coverage analysis.
• Creating and executing test cases to verify functionality in embedded C and SV.
• Identifying, isolating, and debugging issues to drive resolution with design teams.
• Collaborating with cross-functional teams to achieve verification closure and deliverables.

Skills

SystemVerilog/UVM

SystemC/C++

Constrained random

Functional Coverage

HW-SW co-verification

Scripting (Bash/Perl/Python)

Debugging

Education

Master Degree in relevant field

Tools

SystemVerilog/UVM

SystemC/C++

UPF

Formal Verification

Job description

Openchip & Software Technologies S.L. in Rome seeks a Functional Verification Principal Engineer to drive verification across architecture, design and software teams. You will develop high-level models, UVM environments, and HW/SW co-debug capabilities to ensure top performance of complex SoC/IP.

You will mentor teams, coordinate verification activities, and deliver robust verification across emulation and simulation platforms, with strong SystemVerilog, SystemC/C++, and formal techniques.