Senior HF Verification Lead for Optical ICs

Ams Italy S.R.L.; Bardi; On-site; EUR 90,000 - 140,000; Full time

Job summary

ams OSRAM in Pavia, Lombardy, Italy seeks a Principal HF Verification Engineer (d/m/f) to lead verification of broadband optical ICs, focusing on high-frequency mixed-signal interfaces and high-speed datapaths. You will define verification strategies, drive coverage, mentor engineers, and coordinate cross-functional Debug; 10+ years of experience and SystemVerilog/UVM are required.

The role demands advanced CMOS experience (FinFET/FD-SOI) and automation of regression environments in a global

Qualifications

• MSc or PhD in Electrical Engineering.
• 10+ years verification experience.
• SystemVerilog and UVM expertise.
• Broadband optical IC verification with mixed-signal interfaces.
• Coverage-driven verification approach and automation of regression environments.
• Advanced CMOS node experience (FinFET/FD-SOI).

Responsibilities

• Verification leader responsible for defining verification strategies for broadband optical communication ICs, including high-frequency mixed-signal interfaces and high-speed digital datapaths.
• Define verification methodologies and plans.
• Lead block and chip-level verification.
• Drive coverage closure and quality metrics.
• Coordinate cross-functional debug activities.
• Mentor verification engineers.

Skills

SystemVerilog and UVM

Verification leadership

Broadband optical IC verification

High-speed datapaths

Automated regression environments

Cross-functional coordination

Mentoring verification engineers

High-frequency mixed-signal interfaces

FinFET/FD-SOI CMOS experience

Education

MSc or PhD in Electrical Engineering

Job description

ams OSRAM in Pavia, Lombardy, Italy seeks a Principal HF Verification Engineer (d/m/f) to lead verification of broadband optical ICs, focusing on high-frequency mixed-signal interfaces and high-speed datapaths. You will define verification strategies, drive coverage, mentor engineers, and coordinate cross-functional Debug; 10+ years of experience and SystemVerilog/UVM are required.

The role demands advanced CMOS experience (FinFET/FD-SOI) and automation of regression environments in a global