Senior Digital P&R Architect – Timing & PPA Lead

ams Italy S.r.l.; Rho; In loco; EUR 90.000 - 130.000; Tempo pieno

Descrizione del lavoro

ams OSRAM is seeking a highly experienced Digital Backend design expert to lead complex place-and-route activities and develop robust backend flows for cutting-edge CMOS technologies. You will drive timing closure, PPA, and verify physical integrity while mentoring teams across multiple projects.

The role requires a PhD or MSc in Electrical Engineering or Microelectronics, 10+ years in digital backend design, and strong Cadence EDA experience.

Competenze

• MSc or PhD in Electrical Engineering, Microelectronics, or related field.
• 10+ years of experience in digital physical implementation and backend design.
• Proven expertise with industry-standard physical design tools (Cadence EDA preferred).

Mansioni

• Lead place-and-route from synthesis through PnR to sign-off and tape-out.
• Define, deploy, and maintain digital backend methodologies, flows, and best practices.
• Drive timing closure, power, performance, and area (PPA), signal integrity, EM/IR and physical verification strategies.
• Mentor and develop engineers within the digital backend community.
• Lead EDA tool evaluations, methodology improvements, and flow automation initiatives.
• Support technology enablement for advanced CMOS nodes including FinFET and FD-SOI.
• Provide technical leadership across multiple projects and business units.
• Act as interface to foundries, EDA vendors, and methodology teams.
• Drive continuous improvement of backend design efficiency and quality.

Conoscenze

Digital backend design

Timing closure

Power integrity

Mentoring

Leadership

External interface

Formazione

MSc or PhD in Electrical Engineering or Microelectronics

Strumenti

Cadence EDA

Physical design tools

Descrizione del lavoro

ams OSRAM is seeking a highly experienced Digital Backend design expert to lead complex place-and-route activities and develop robust backend flows for cutting-edge CMOS technologies. You will drive timing closure, PPA, and verify physical integrity while mentoring teams across multiple projects.

The role requires a PhD or MSc in Electrical Engineering or Microelectronics, 10+ years in digital backend design, and strong Cadence EDA experience.