Principal HS Digital Place & Route Engineer (d/m/f)

Ams Osram; Italia; In loco; EUR 90.000 - 130.000; Tempo pieno

Descrizione del lavoro

ams OSRAM is seeking a Technical Expert in physical design within the LSP unit to advance high-speed digital and mixed-signal blocks for communication ICs.

You will own place-and-route implementation activities, define design methodologies, and optimize PPA, timing closure and signal integrity while coordinating sign-off and supporting tape-out execution.

Competenze

• MSc in Electrical Engineering.
• 10+ years physical design experience.

Mansioni

• Own place-and-route implementation activities.
• Define physical design methodologies.
• Optimize PPA, timing closure and signal integrity.
• Coordinate implementation sign-off.
• Support tape-out execution.

Conoscenze

Physical design

Place-and-route

PPA optimization

Timing closure

Signal integrity

High-speed interfaces

Formazione

MSc in Electrical Engineering

10+ years physical design experience

Strumenti

Place-and-route tools

STA

Physical verification

Floorplanning

CTS

IR-drop analysis

EM analysis

Descrizione del lavoro

We are LSP – Light Sensors & Photonics, one of three business units within ams OSRAM, advancing the digitalization of light. At LSP, we go beyond traditional sensing—combining light, silicon, and system expertise to enable digital photonics solutions. Our focus is clear: powering next-generation applications in data centers, AR/VR, mobile and automotive, where light becomes a critical interface for data, perception, and interaction. This evolution marks a shift from components to integrated photonics systems —driving performance, scalability, and innovation in high-growth segments.

• Technical expert responsible for physical implementation of high-speed digital and mixed-signal blocks for communication ICs
• Own place-and-route implementation activities
• Define physical design methodologies
• Optimize PPA, timing closure and signal integrity
• Coordinate implementation sign-off
• Support tape-out execution

• MSc in Electrical Engineering
• 10+ years physical design experience
• Place-and-route tools
• STA and physical verification
• Floorplanning, CTS, IR-drop and EM analysis
• Advanced CMOS node experience, including FinFET and/or FD-SOI, is required
• Physical implementation experience for high-speed digital or mixed-signal ICs is required; implementation awareness of high-speed interfaces such as UCIe, PCIe or similar protocols is an advantage