NAND Datapath Design Engineer - High-Speed CMOS & DDR

Micron Technology, Inc.; Avezzano; On-site; EUR 34,000 - 57,000; Full time

Benefits offered by this job

Meal vouchers

Corporate welfare

Remote working days (annual allowance)

Supplementary health insurance

Life coverage

Employee Assistance Program

Job summary

Micron Technology, Inc. in Italy seeks a Design/Senior Design Engineer for NAND datapath development. You will contribute to datapath architectures and high‑speed interfaces, working on block and sub‑system levels to enable full‑chip integration.

You will apply your expertise in CMOS timing, signal integrity and power optimization, using industry tools and Micron methodologies, collaborating across teams to ensure robust designs.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• Strong knowledge of high-speed digital, analog, and mixed-signal CMOS circuit design.
• Solid understanding of timing, signal integrity, noise, variability, and deep-submicron device effects.

Responsibilities

• Design and optimize high-speed datapath and interface circuits, ensuring timing closure at block and sub-system levels.
• Translate requirements into circuit architectures and transistor-level implementations, balancing performance, power, and area.
• Perform functional, timing, and signal integrity verification with advanced simulations (PVT/corners).
• Collaborate with cross-functional teams for floorplan integration, manufacturability, and product specs alignment.
• Develop and apply automation solutions (scripting, AI-assisted methods) and support silicon validation and debugging.

Skills

CMOS design

Timing analysis

RTL Verilog

SPICE simulation

Cross-functional teamwork

Education

MS or PhD in Electrical Engineering

Tools

Python scripting

Layout constraints tools

Job description

Micron Technology, Inc. in Italy seeks a Design/Senior Design Engineer for NAND datapath development. You will contribute to datapath architectures and high‑speed interfaces, working on block and sub‑system levels to enable full‑chip integration.

You will apply your expertise in CMOS timing, signal integrity and power optimization, using industry tools and Micron methodologies, collaborating across teams to ensure robust designs.