Senior Analog IC Layout Architect for MCU

NXP Semiconductors; Catania; In loco; EUR 51.000 - 70.000; Tempo pieno

Descrizione del lavoro

NXP Semiconductors is seeking a Senior Layout Engineer to drive physical implementation of complex analog, mixed-signal ICs from floorplanning to tape-out.

You will collaborate across design, verification, and technology teams, mentor junior engineers, and help mitigate risks to ensure silicon delivers on performance and reliability. Fluent English required; extensive Cadence experience expected.

Competenze

• 8–12+ years of custom analog/mixed-signal layout experience in deep sub-micron CMOS.
• Expertise with Cadence Virtuoso XL and layout methodologies.
• Fluent in English; strong cross-functional communication.
• Experience leading layouts and mentoring junior engineers.

Mansioni

• Lead the layout implementation of complex analog, mixed-signal, and custom digital blocks.
• Drive floorplanning, device matching, routing strategies, and layout optimization.
• Perform and review physical verification activities (DRC, LVS, ERC, EM/IR).
• Collaborate with design, verification, technology, and product teams to meet milestones.
• Support advanced-node technologies and contribute to methodology improvements.
• Provide guidance and mentorship to junior engineers and contractors.
• Assess project risks and drive execution to meet schedules.

Conoscenze

Cadence Virtuoso XL

Floorplanning

Device matching

High-speed routing

Formazione

BSEE or MSEE

Strumenti

PVS DRC/LVS/ERC

Descrizione del lavoro

NXP Semiconductors is seeking a Senior Layout Engineer to drive physical implementation of complex analog, mixed-signal ICs from floorplanning to tape-out.

You will collaborate across design, verification, and technology teams, mentor junior engineers, and help mitigate risks to ensure silicon delivers on performance and reliability. Fluent English required; extensive Cadence experience expected.