Manager, Test Engineering - HV Power ICs

Allegro Microsystems

Lazio

In loco

EUR 70.000 - 95.000

Tempo pieno

4 giorni fa
Candidati tra i primi
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Descrizione del lavoro

Allegro MicroSystems in Milan, Italy seeks a Manager, Test Engineering to lead a team of Test Development and Product Validation Engineers. You own test strategy, wafer probe and final test, and drive DFT collaboration across design and systems engineering.

You’ll ensure quality, reliability, and manufacturability of our high‑voltage IC portfolio for automotive and industrial sectors. Strong leadership, deep ATE knowledge, and experience with ISO 26262/AEC‑Q100 are required, with global

Competenze

  • Bachelor’s or Master’s degree in Electrical/Electronic Engineering.
  • 8+ years in semiconductor Test Engineering with analog/mixed-signal/high-voltage power IC testing.
  • Experience leading teams or projects in a technical environment.
  • Strong scripting skills in Python and/or C/C++ for data analysis.

Mansioni

  • Lead, mentor, and grow a team of Test Development and Product Engineers.
  • Define, develop, and implement test strategies for high-voltage ICs (wafer probe and final test).
  • Oversee ATE hardware/software development and test programs (Teradyne platforms).
  • Collaborate on DFT methodologies early in the product lifecycle.
  • Drive silicon characterization and transition from PPR to RTP in production.

Conoscenze

Test engineering
ATE
Python
C/C++
Leadership

Formazione

Electrical Engineering degree

Strumenti

Teradyne ETS/Eagle 364
PCB test boards

Descrizione del lavoro

Allegro MicroSystems in Milan, Italy seeks a Manager, Test Engineering to lead a team of Test Development and Product Validation Engineers. You own test strategy, wafer probe and final test, and drive DFT collaboration across design and systems engineering.

You’ll ensure quality, reliability, and manufacturability of our high‑voltage IC portfolio for automotive and industrial sectors. Strong leadership, deep ATE knowledge, and experience with ISO 26262/AEC‑Q100 are required, with global

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