Lead of Silicon Design Support Infrastructure

FONDAZIONE CHIPS-IT; Cascina Vignazza; In loco; EUR 90.000 - 130.000; Tempo pieno

Descrizione del lavoro

Fondazione Chips-IT seeks a Lead of Silicon Design Support Infrastructure to establish and head a multi-domain design, validation and test infrastructure group. Based in Italy, the role will enable demonstrator development across digital, analog and power IC domains for internal teams and external partners.

The role requires building a capable team (5–10 engineers/technicians), managing EDA tools licenses, computing resources, and end-to-end workflows from architecture to tape-out, with a strong

Competenze

• Proven leadership of multi-domain silicon infrastructure projects.
• Experience in set-up and governance of engineering infrastructure teams.
• Strong understanding of digital, analog, and power IC design workflows.

Mansioni

• Set up and lead the Silicon Infrastructure Group, including 3-year budget forecasting.
• Define personnel profiles and recruitment plan (initially 5–10 hires).
• Manage licensing, compliance, and vendor relationships for multi-domain EDA tools.
• Oversee data security and IP protection for design data across projects.
• Run test facilities and safety programs for digital, analog, and power domains.
• Support technical roadmaps and resource allocation for silicon demonstrations from architecture to tape-out.
• Establish common design methodologies and best practices across groups.
• Coordinate collaboration infrastructure with universities and industry partners.
• Scout technology and coordinate pilot implementations with foundries and tools.

Conoscenze

EDA Tool Mgmt

Compute Infrastruct.

Workflow Automation

Design Tools Evaluation

Test & Validation

Strumenti

EDA Licenses (Synopsys, Cadence, Siemens, Keysight)

Descrizione del lavoro

Fondazione Chips-IT is seeking a Lead of Silicon Design Support Infrastructure to establish and lead the Design, Validation and Test Infrastructure Group. This Group will enable multi-domain semiconductor demonstrator development (Digital, Analog, Power) supporting internal research teams and collaborations with university and industry partners.

The Group will have a central role in the operation of Chips-IT, providing the best possible environment for Research Groups to develop their projects. Its capabilities should bring the Foundation to demonstration levels of TRL 5 to 7 depending on the projects, while also providing infrastructure access for academic and industrial partners within established collaboration frameworks.

The work can be carried out either in Pavia or in Bologna.

KEY RESPONSIBILITIES

Set-Up of the Group

• In coordination with the Research Groups Directors, will define and propose to the CEO the organisation of the Silicon Infrastructure Group and present a 3-year budget forecast
• Together with the HR Manager, will define the profiles of the personnel, engineers and technicians, to recruit (initially between 5 and 10 people)
• It is expected that the infrastructure will provide the following:

1. EDA Tool Management: Installing, maintaining, and upgrading EDA software licenses from vendors like Synopsys, Cadence, Siemens, and Keysight for digital, analog, mixed-signal, and power IC design
2. Computing Infrastructure Optimization: Managing computing environments, including compute clusters, storage, and networking, to support compute-intensive design and simulation workloads across digital, analog, and power domains
3. Workflow Automation: Continuously developing and optimizing multi-domain design workflows from architecture through tape-out, using advanced tools and techniques to enable efficient silicon demonstrator development
4. Advanced Design Tools: Evaluating and enabling cutting-edge design automation tools and methodologies across all semiconductor domains to accelerate development cycles and enhance design quality
5. Emulation and Pre-Silicon Validation: Providing emulation infrastructure for digital designs and supporting hardware-software co-design for demonstrators
6. Multi-Domain Test Facility: Providing comprehensive test capabilities across digital, analog, and power domains including:
   • Silicon characterization for digital, analog, and mixed-signal ICs
   • Power electronics validation (power analyzers, high-voltage benches, thermal characterization
   • RF/analog measurement infrastructure (network/spectrum analyzers, precision equipment)
   • Lab automation and safety compliance for all test domains
   • Foundry and Fabrication Coordination: Managing foundry relationships, PDK installations, tape-out scheduling, shuttle run organization, and post-silicon debug support across all technology domains

Management of the Group

• Licensing and Compliance: Managing software licensing costs, compliance, and vendor relationships for multi-domain EDA tools
• Data Management & Security: Ensuring security for sensitive design data and managing IP (Intellectual Property) for design reuse across digital, analog, and power projects
• Test Facility Management and Safety: Ensuring that the test facility supports multi-domain silicon validation and demonstration needs (digital, analog, power), optimizing lab utilization and guaranteeing safety standards including high-voltage compliance
• Technical Roadmap Support: Support the Foundation Management in defining technical roadmaps and resource allocation to ensure infrastructure enables multi-domain silicon demonstration objectives from architecture through tape-out and validation
• Methodology Governance: Establish and maintain common design methodologies and best practices across research groups in all semiconductor domains to ensure efficient IP reuse and design optimization
• Collaboration Infrastructure Management: Establishing and managing shared access policies for university and industry partners, including remote access to tools and computing resources, IP protection frameworks, and multi-party project coordination
• Technology Scouting and Assessment: Continuously monitoring emerging technologies, tools, and methodologies across digital, analog, and power domains to identify potential enablers for research projects, evaluating their applicability and coordinating pilot implementations
• Technical Relations with Foundries: Building and maintaining strategic relationships with foundry partners, technology providers to ensure access to cutting-edge processes for all semiconductor domains
• Proactive Research Support: Support the Research Groups in their multi-domain silicon development projects in a proactive manner, leveraging deep semiconductor experience to ensure common approaches, methodology alignment, and resource optimization