Lead of Silicon Design Support Infrastructure

Fondazione Chips-IT; Bologna; In loco; EUR 90.000 - 140.000; Tempo pieno

Vantaggi offerti da questo lavoro

Lunch tickets

Private health care coverage

Hybrid work policy

PhD conjugation opportunity

Descrizione del lavoro

Fondazione Chips-IT is seeking a Lead of Silicon Design Support Infrastructure to establish and lead the Design, Validation and Test Infrastructure Group. This role enables multi-domain demonstrator development and supports internal research teams with university and industry partners.

The successful candidate will oversee EDA/tool management, computing infrastructure, and foundry coordination, driving a 3-year budget plan and establishing the group in Bologna or Pavia, Italy.

Competenze

• 15+ years in R&D or product development in semiconductor sector.
• Experience leading multi-skilled groups and pre-production projects.
• Willingness to establish a new activity within a research environment.

Mansioni

• Define and propose the Silicon Infrastructure Group organization.
• Recruit and profile personnel (initially 5–10 engineers/technicians).
• Provide infrastructure for EDA, computing, workflow automation, and test facility operations.
• Manage licensing, data security, safety, and collaboration with foundries.

Conoscenze

EDA infrastructure

Leadership & team management

Budgeting & strategic planning

Design-for-manufacturability

Cross-domain silicon design

Formazione

Engineering degree in a relevant field

PhD (advantage)

Strumenti

RTL design tools

Analog/RF design tools

EDA tool management

Silicon validation & test infrastructure tools

Descrizione del lavoro

The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.

The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a centre of excellence in frontier research on semiconductor design, as well as a pivotal centre of the Italian semiconductor ecosystem and expertise.

Posizione

Fondazione Chips-IT is seeking a Lead of Silicon Design Support Infrastructure to establish and lead the Design, Validation and Test Infrastructure Group. This Group will enable multi-domain semiconductor demonstrator development (Digital, Analog, Power) supporting internal research teams and collaborations with university and industry partners.

The Group will have a central role in the operation of Chips-IT, providing the best possible environment for Research Groups to develop their projects. Its capabilities should bring the Foundation to demonstration levels of TRL 5 to 7 depending on the projects, while also providing infrastructure access for academic and industrial partners within established collaboration frameworks.

The work can be carried out either in Pavia or in Bologna.

Key Responsibilities

• In coordination with the Research Groups Directors, define and propose to the CEO the organisation of the Silicon Infrastructure Group and present a 3‑year budget forecast.
• Together with the HR Manager, define the profiles of the personnel, engineers and technicians, to recruit (initially between 5 and 10 people).
• Provide the infrastructure for: EDA Tool Management, Computing Infrastructure Optimization, Workflow Automation, Advanced Design Tools, Emulation and Pre‑Silicon Validation, Multi‑Domain Test Facility, Foundry and Fabrication Coordination.
• Manage licensing and compliance, data management & security, test facility safety, technical roadmap support, methodology governance, collaboration infrastructure management, technology scouting, technical relations with foundries, and proactive research support.

Requisiti

The candidate is a semiconductor sector professional with at least 15 years of industrial experience in R&D or product development and with a broad set of knowledge and skills. He/She has already managed multi‑skilled groups and led development projects in the pre‑production phase and is willing to take the challenge of fully setting up a new activity in a research environment.

In particular, He/she will have

• Knowledge of EDA infrastructure – familiarity with RTL design, logic synthesis, analog and RF design, physical design, and simulation tools for complete design‑to‑silicon flows across digital, analog, and power domains.
• Knowledge of test facility infrastructure – familiarity with silicon characterization equipment, lab automation, instrumentation for post‑silicon validation, safety procedures and compliance requirements.
• Power electronics infrastructure – familiarity with test equipment and methodologies specific to power management ICs, DC‑DC converters, AC‑DC conversion, high‑voltage safety compliance and thermal validation.
• Analog/Mixed‑Signal test capabilities – understanding of analog and RF characterization requirements, measurement equipment, and validation methodologies for mixed‑signal demonstrators.
• Silicon design flow understanding – understanding of ASIC/SoC development from specification through tape‑out, including familiarity with foundry processes, PDKs, and design for manufacturability.
• Foundry ecosystem knowledge – experience with foundry processes, PDK management, tape‑out coordination, and understanding of semiconductor manufacturing.

Altre Informazioni

WHAT WE OFFER

• Competitive compensation and contract type, to be negotiated based on qualifications and experience.
• Possibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title.
• Lunch tickets.
• Private health care coverage depending on your role and contract.
• Structured growth path, with ongoing access to training and updates.
• Networking opportunities with industry‑leading professionals.
• International environment.
• Hybrid work policy.
• Tax deductions: Candidates from abroad may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years.