Digital Backend Engineer – ASIC/SoC Physical Design

Move Silicon

Toscana

Hybrid

EUR 34,000 - 48,000

Full time

6 days ago
Be an early applicant

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Benefits offered by this job

Mensa interna
Buoni pasto
Assicurazione sanitaria
Bonus annuale
Formazione EDA

Job summary

Move Silicon cerca un Digital Backend Engineer per un nuovo team di ingegneri dedicato al backend fisico di ASIC/SoC, con focus su RTL-to-GDS, floorplanning, P&R e timing closure. Lavorerai in stretto contatto con i team di design e foundry.

Offriamo contratto a tempo indeterminato, sede a Milano con possibilità di smart working e Lucca, formazione continua su tool EDA, bonus legato ai risultati e benefit.

Qualifications

  • Laurea magistrale in Ingegneria Elettronica o Informatica.
  • 4-5 anni di esperienza in backend/physical design ASIC/SoC.
  • Padronanza di Innovus/ICC2/Aprisa e PrimeTime/Tempus.
  • Competenze di CTS, STA, DRC/LVS e chiusura timing multi-corner.
  • Capacità di scripting in TCL/Python e uso di Git.

Responsibilities

  • Synthesis e floor-planning a partire da netlist RTL, definendo macro placement, channel e power grid.
  • Place-&-Route (Cadence Innovus, Synopsys ICC2/ Fusion Compiler, Siemens Aprisa) con focus su congestione, timing e DRC.
  • Clock-Tree Synthesis (CTS) e ottimizzazione di skew, jitter e insertion delay.
  • Static Timing Analysis (STA) con PrimeTime o Tempus, chiusura di hold/set-up e path criticali multi-corner.
  • Power e IR-drop analysis, integrazione di tecniche low-power (UPF, DVFS, power gating).

Skills

backend/physical design
Scripting TCL/Python
Git

Education

Laurea magistrale in Ingegneria Elettronica/Informatica

Tools

Innovus
ICC2
Aprisa
PrimeTime
Tempus
TCL
Python

Job description

Move Silicon cerca un Digital Backend Engineer per un nuovo team di ingegneri dedicato al backend fisico di ASIC/SoC, con focus su RTL-to-GDS, floorplanning, P&R e timing closure. Lavorerai in stretto contatto con i team di design e foundry.

Offriamo contratto a tempo indeterminato, sede a Milano con possibilità di smart working e Lucca, formazione continua su tool EDA, bonus legato ai risultati e benefit.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Digital Backend Engineer – Physical Design & Sign-off - Milano
Digital Backend Engineer – Physical Design & Sign-off - Milano

Move Silicon • Lombardia

Hybrid
EUR 38,000 - 53,000
Bonus annuale
Mensa interna
Assicurazione sanitaria
+1
Senior Digital Backend Engineer – ASIC Sign-off & P&R
Senior Digital Backend Engineer – ASIC Sign-off & P&R

Move Silicon • Lombardia

Hybrid
EUR 38,000 - 53,000
Bonus annuale
Mensa interna
Assicurazione sanitaria
+1
Digital Backend Engineer – Physical Design & Sign-off - Lucca
Digital Backend Engineer – Physical Design & Sign-off - Lucca

Move Silicon • Toscana

Hybrid
EUR 34,000 - 48,000
Mensa interna
Buoni pasto
Assicurazione sanitaria
+2
Analog IC Engineer – FinFET Design
Analog IC Engineer – FinFET Design

Move Silicon • Toscana

Hybrid
EUR 30,000 - 38,000
Contratto a tempo indeterminato
Mentorship senior FinFET
Accesso a conferenze (ISSCC, A-SSCC)
+3
Soc Physical Design Engineer
Soc Physical Design Engineer

Nokia • Terni

Hybrid
EUR 65,000 - 100,000
Flexible and hybrid working schemes
Parental leave (90 days)
Life insurance for employees
+3
Analog IC Engineer – FinFET Design
Analog IC Engineer – FinFET Design

Move Silicon • Lombardia

Hybrid
EUR 32,000 - 42,000
Smart working ibrido
Mensa interna / buoni pasto
Assicurazione sanitaria
+1
Lead of Silicon Design Support Infrastructure
Lead of Silicon Design Support Infrastructure

Fondazione Chips-IT • Bologna

On-site
EUR 90,000 - 140,000
Lunch tickets
Private health care coverage
Hybrid work policy
+1
Senior Physical Design Engineer - Hybrid SoC Leader
Senior Physical Design Engineer - Hybrid SoC Leader

Fondazione Chips-IT • Cascina Priora

Hybrid
EUR 25,000 - 55,000
Compensazione competitiva
Pranzo a carico dell'azienda
Copertura sanitaria privata
Head of Silicon Design & Validation Infrastructure
Head of Silicon Design & Validation Infrastructure

Fondazione Chips-IT • Bologna

On-site
EUR 90,000 - 140,000
Soc Physical Design Engineer
Soc Physical Design Engineer

Nokia • Macerata

Hybrid
EUR 60,000 - 90,000
Flexible work arrangement
Parental leave
Life insurance
+3