Design Verification Engineer SoC

Fondazione Chips-IT; Cascina Priora; Ibrido; EUR 25.000 - 55.000; Tempo pieno

Vantaggi offerti da questo lavoro

Lunch tickets

Private health care

Structured growth path

International environment

Hybrid work policy

Descrizione del lavoro

Fondazione Chips-IT è un ente nonprofit che guida la ricerca nei semiconduttori. Cerchiamo un Verification Engineer esperto per sviluppare e validare IP digitali e piattaforme SoC, creando ambienti di verifica con UVM e garantendo correttezza dalla specifica al tape-out.

Lavoro possibile a Pavia o Bologna. Requisiti: laurea magistrale in Ingegneria Elettronica o Informatica e almeno 5 anni di verifica digitale, SystemVerilog e UVM, strumenti di simulazione (QuestaSim, VCS, Verdi) e conoscenza

Competenze

• Laurea magistrale in Ingegneria Elettronica, Informatica o livello equivalente.
• Almeno 5 anni di esperienza in verifica digitale.
• Conoscenza approfondita di SystemVerilog e metodologia UVM.
• Esperienza con simulazione e debug (QuestaSim, VCS, Verdi).
• Conoscenza di protocolli AMBA AXI/APB/AHB.
• Capacità di scrivere testbench vincolati e analizzare metriche di coverage.
• Buona comprensione di design digitale, architettura SoC e RTL.

Mansioni

• Definire e implementare strategie di verifica a livelli IP e SoC.
• Sviluppare ambienti di verifica basati su UVM, testbench e coverage funzionale.
• Progettare ed eseguire piani di test allineati a specifiche.
• Debug di RTL e problemi di simulazione con tool avanzati.
• Integrare componenti di verifica e garantire complete test coverage.
• Contribuire a l'infrastruttura di regression e automatizzare esecuzioni.
• Collaborare strettamente con RTL designers, DFT e team di implementazione fisica.
• Supportare attivita' di bring-up post-silicon.

Conoscenze

SystemVerilog

UVM

Digital design verification

Teamwork

Formazione

Master in Electrical Engineering

Strumenti

QuestaSim

VCS

Verdi

AMBA AXI

APB

AHB

Descrizione del lavoro

About Fondazione Chips-IT

Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry. The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal centre of the Italian semiconductor ecosystem and expertise.

Missions Of The Foundation

• Promote the design and development of integrated circuits
• Strengthen the system of professional training in the field of microelectronics
• Ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field

Posizione

We are seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape‑out. The position also involves collaboration with design, architecture, and software teams to deliver reliable and high-quality silicon. The work can be carried out either in Pavia or in Bologna.

Key Responsibilities

• Define and implement verification strategies at IP and SoC levels.
• Develop and maintain UVM-based verification environments, including testbenches and functional coverage.
• Design and execute test plans aligned with design specifications and requirements.
• Debug RTL and simulation issues using advanced tools and techniques.
• Integrate verification components and ensure complete test coverage.
• Contribute to regression infrastructure and manage automated test execution.
• Collaborate closely with RTL designers, DFT engineers, and physical implementation teams.
• Support post‑silicon bring‑up and validation activities as needed.

Requisiti

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 5 years of experience in digital design verification.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands‑on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi).
• Familiarity with industry‑standard protocols such as AMBA AXI, APB, and AHB.
• Experience in writing constrained‑random testbenches and analyzing coverage metrics.
• Good understanding of digital design, SoC architecture, and RTL development.
• Strong teamwork, communication, and documentation skills.

Altre Informazioni

WHAT WE OFFER:

• Competitive compensation and contract type, to be negotiated based on qualifications and experience.
• Possibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title.
• Lunch tickets.
• Private health care coverage depending on your role and contract.
• Structured growth path, with ongoing access to training and updates.
• Networking opportunities with industry‑leading professionals.
• International environment.
• Hybrid work policy.
• Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years.

In conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione è compreso tra Euro 25.000,00 e 55.000,00. L'ampiezza del range è finalizzata a valutare candidature con diversi livelli di seniority; l'offerta finale sarà strettamente commisurata all’effettiva esperienza e alle competenze del candidato, e sarà integrata dai benefit aziendali previsti per il ruolo.