Wireless Verification Engineers

Cyient Limited; Hyderabad; On-site; INR 1,562,000 - 3,125,000; Part time

Job summary

Silicon Labs seeks a Design Verification contractor to support verification of next-generation Wi-Fi and Low Power Wireless SoCs. The engineer will work independently on UVM-based verification, regression debugging, and SoC/RF interface validation.

Required skills include SystemVerilog/UVM, SV, C, RTL/GLS debugging, constrained-random verification, functional coverage and SVA, plus experience with Verdi/DVE/SimVision. Onsite in Hyderabad, 6–10 years experience preferred.

Qualifications

• 6–10 years of ASIC/SoC Design Verification experience.
• Expertise in SystemVerilog (SV) and UVM.
• Strong C programming skills.
• Experience in RTL and Gate-Level Simulation (GLS) debug.
• Experience in constrained-random verification, functional coverage and SystemVerilog Assertions (SVA).
• Strong debugging skills with Verdi/DVE/SimVision.
• Experience in Wi-Fi and/or Low Power Wireless (BLE, Zigbee, Thread, Matter) verification.
• Ability to debug protocol, subsystem and SoC-level failures independently.
• Good understanding of digital design fundamentals and SoC architecture.

Responsibilities

• Develop and maintain UVM verification environments.
• Develop test plans, testcases, sequences, scoreboards and assertions.
• Execute RTL and GLS regressions and perform root-cause analysis.
• Debug RF interface, protocol and integration issues.
• Work closely with RTL, Firmware, Architecture and Validation teams.
• Drive closure of verification issues with high quality.

Skills

SystemVerilog & UVM

C programming

RTL/GLS debugging

Constrained-random verification

Functional coverage & SVA

Verdi/DVE/SimVision

Wi-Fi/LPW verification

protocol/SoC debugging

SoC architecture knowledge

Tools

VCS/Xcelium/Questa

Git

Jenkins

Python scripting

MATLAB/Simulink

CDC/RDC/SDF timing debug

Job description

Contractor Requirement – Design Verification Engineer (Wi-Fi / Low Power Wireless)

Customer: Silicon Labs
Experience: 6–10 Years
Location: Hyderabad (Onsite)
Positions: 2

Project Overview

Silicon Labs is looking for a Design Verification contractor to support verification of next-generation Wi-Fi and Low Power Wireless (LPW) SoCs. The engineer is expected to work independently on UVM-based verification, regression debug, and SoC/RF interface validation.

Mandatory Technical Skills

• 6–10 years of ASIC/SoC Design Verification experience.
• Expertise in SystemVerilog (SV) and UVM.
• Strong C programming skills.
• Experience in RTL and Gate-Level Simulation (GLS) debug.
• Experience in constrained-random verification, functional coverage and SystemVerilog Assertions (SVA).
• Strong debugging skills with Verdi/DVE/SimVision.
• Experience in Wi-Fi and/or Low Power Wireless (BLE, Zigbee, Thread, Matter) verification.
• Ability to debug protocol, subsystem and SoC-level failures independently.
• Good understanding of digital design fundamentals and SoC architecture.

Preferred Skills

• RF interface debug and digital/RF integration knowledge.
• PHY/MAC architecture understanding.
• DSP fundamentals and communication systems knowledge.
• MATLAB/Simulink exposure for algorithm understanding.
• Python scripting for automation.
• Experience with VCS/Xcelium/Questa, Git and Jenkins.
• Experience with CDC/RDC and SDF timing debug ($setuphold, $recrem).

Roles & Responsibilities

• Develop and maintain UVM verification environments.
• Develop test plans, testcases, sequences, scoreboards and assertions.
• Execute RTL and GLS regressions and perform root-cause analysis.
• Debug RF interface, protocol and integration issues.
• Work closely with RTL, Firmware, Architecture and Validation teams.
• Drive closure of verification issues with high quality.

Vendor Expectations

• 30 days notice period expected.
• Profiles should be pre-screened before submission.
• Submit updated resume highlighting relevant wireless verification experience.
• Candidate should be willing to work onsite from Hyderabad.