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Logicsemi Technologies Pvt Ltd in Hyderabad, India, seeks an experienced Functional Verification Engineer to lead ASIC/SoC verification efforts. You will build robust UVM-based testbenches and drive coverage closure in a fast-paced semiconductor environment.
Ideal candidates have 6+ years of VLSI verification, deep SystemVerilog/UVM expertise, and AMBA protocol knowledge. This on-site role offers competitive compensation and strong opportunities for technical leadership.
Driving advanced silicon verification and high-performance semiconductor design validation, Logicsemi Technologies Pvt Ltd is actively expanding its engineering division with an opening for an accomplished Functional Verification Engineer in Hyderabad. In this critical design verification role, you will architect, build, and maintain robust UVM-based testbenches, verify complex ASIC and SoC designs, and ensure absolute compliance with microarchitectural specifications. Bringing over six years of dedicated VLSI verification experience and deep mastery of SystemVerilog, UVM, and AMBA protocols, you will empower our team to deliver flawless silicon solutions. This career opportunity offers competitive remuneration, technical visibility, and exceptional professional growth within a premier semiconductor engineering enterprise.
As a Functional Verification Engineer supporting Logicsemi Technologies in Hyderabad, India, you will take full operational, architectural, and tactical ownership of ASIC/SoC functional verification, testbench development, and coverage closure. Your day-to-day responsibilities include developing and maintaining reusable UVM-based verification environments, authoring comprehensive verification plans, test scenarios, and directed/constrained-random test cases, and implementing drivers, monitors, scoreboards, and sequences. You will execute regression management, perform detailed debugging and root-cause analysis of functional failures, and verify AMBA protocol compliance (AXI/AHB/APB).
Contract Duration: Permanent / Full-Time On-Site Engagement (Hyderabad)
Notice Period: Immediate to 30 Days Preferred
Salary/Rate: Market Competitive / Enterprise VLSI Engineering Package
Deadline: Open until filled (Urgent Hyderabad Verification Opening)