Lead Engineer – IC Verification

Silicon Labs; Hyderabad; Sur place; INR 3 500 000 - 6 500 000; Plein temps

Résumé du poste

Silicon Labs invites an experienced Lead IC Verification Engineer to join the Modem team and verify digital baseband and PHY-layer IPs for wireless SoCs and Wi‑Fi/IOT applications.

You will develop robust SystemVerilog/UVM environments, drive coverage closure, and integrate C-based reference models for bit-exact verification while collaborating with RTL designers and systems teams to ensure timely IP delivery.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Communication Engineering, or a related field.
• 7–15 years of RTL Design Verification experience, ideally with mixed-signal datapath or PHY-layer modules.
• Strong SystemVerilog and UVM verification knowledge.
• Experience developing UVM testbench components: agents, drivers, monitors, scoreboards, and coverage models.
• Experience with constrained-random testing, functional coverage, and coverage closure.
• Experience integrating C-based reference models for bit-exact verification.

Responsabilités

• Develop and maintain SystemVerilog/UVM verification environments for modem digital baseband and PHY-layer IPs.
• Design and implement module- and subsystem-level testbenches, including drivers, monitors, agents, scoreboards, and coverage models.
• Define and execute comprehensive verification plans to ensure functional correctness and design quality.
• Drive constrained-random verification, functional coverage, and coverage closure.
• Perform bit-exact verification by integrating C-based reference models into verification environments.
• Verify complex mixed-signal datapath and PHY-layer modules used in wireless communication systems.
• Debug complex RTL and testbench issues, collaborating with design and systems teams to identify root causes.
• Collaborate across teams to resolve integration challenges and ensure IP verification and delivery.
• Participate in design reviews and continuous improvement of verification methodologies.

Connaissances

SystemVerilog

UVM verification

Mixed-signal datapath

Bit-exact verification

Debugging & problem-solving

Cross-functional collaboration

Formation

Bachelor's or Master's in Electrical/Electronics/Communication

Outils

C-based reference models

Description du poste

In this role, you will work on verifying complex digital RTL blocks within wireless modem baseband and PHY-layer subsystems that power Wi‑Fi and low‑power IoT devices. You will play a key role in ensuring the functional correctness, performance, and reliability of modem IPs used in Silicon Labs' wireless SoCs.

This is a great opportunity for an experienced Design Verification Engineer who enjoys solving complex technical challenges, developing robust verification environments, and working closely with design and systems teams to deliver high-quality wireless solutions.

Meet the Team

Our Modem team develops digital baseband and PHY‑layer IPs that enable wireless connectivity across Wi‑Fi and low‑power IoT applications.

As part of this team, you will collaborate closely with RTL designers, modem system engineers, verification engineers, and SoC teams to verify complex modem IPs and ensure seamless integration into wireless SoCs.

Responsibilities

As a Lead IC Verification Engineer on the Modem team, you will:

• Develop and maintain SystemVerilog/UVM-based verification environments for modem digital baseband and PHY‑layer IPs.
• Design and implement module-level and subsystem-level testbenches, including drivers, monitors, agents, scoreboards, and coverage models.
• Define and execute comprehensive verification plans to ensure functional correctness and design quality.
• Drive constrained‑random verification, functional coverage, and coverage closure.
• Perform bit‑exact verification by integrating C-based algorithmic reference models into verification environments.
• Verify complex mixed‑signal datapath and PHY‑layer modules used in wireless communication systems.
• Debug complex RTL and testbench issues, working closely with design and system engineering teams to identify root causes.
• Collaborate across functional teams to resolve integration challenges and ensure successful IP verification and delivery.
• Participate in design reviews, verification planning, and continuous improvement of verification methodologies.

Skills You Will Need

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Communication Engineering, or a related field.
• 7–15 years of experience in RTL Design Verification, preferably involving mixed‑signal datapath, modem baseband, or PHY‑layer modules.
• Strong hands‑on expertise in SystemVerilog and UVM verification methodologies.
• Experience developing UVM testbench components such as agents, drivers, monitors, scoreboards, and coverage models.
• Strong understanding of constrained‑random testing, functional coverage, and coverage closure.
• Experience integrating C‑based reference models for bit‑exact functional verification.
• Good understanding of digital communication systems and PHY‑layer concepts.
• Strong debugging, problem‑solving, and cross‑functional collaboration skills.

Skills That Will Make You Stand Out

• Experience with IEEE 802.11 Wi‑Fi, 4G/5G cellular, or other OFDM‑based communication systems.
• Hands‑on experience verifying wireless modem baseband and digital signal processing IPs.
• Knowledge of DSP blocks such as FFT, FIR filters, correlators, and FEC decoders.
• Experience working with mixed‑signal verification environments and digital/analog interfaces.
• Experience with subsystem‑level verification and integration of complex IPs into wireless SoCs.
• Ability to independently own verification activities and drive complex debugging and coverage closure.

"Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision‑making"

At Silicon Labs, you’ll be part of a highly skilled team where every engineer makes a meaningful impact. We promote work‑life balance and a welcoming, fun environment.