Wireless Design Verification Engineers

Purna Semi; Bengaluru; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

Purna Semi in Bangalore is seeking experienced Wireless Design Verification Engineers to support verification of next-generation Wi-Fi and LPW SoCs. You will develop and maintain SystemVerilog/UVM-based verification environments and execute RTL/GLS regressions.

The ideal candidate will work independently on UVM-based verification, regression debug, protocol validation, and SoC/RF interface integration, collaborating with RTL Design, Firmware, Architecture, RF, and Validation teams to ensure high

Qualifications

• 6–10 years of experience in wireless design verification.
• Strong knowledge of SystemVerilog/UVM verification environments.
• Experience with RTL and Gate-Level Simulation (GLS) regressions.
• Independent regression debugging and root-cause analysis.
• Experience with Wi-Fi and Low Power Wireless SoCs.
• Collaborative work with RTL, Firmware, Architecture, RF teams.

Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments.
• Create detailed verification plans, test cases, sequences, scoreboards, checkers, and assertions.
• Execute RTL and GLS regressions.
• Analyze regression failures and perform root-cause analysis.
• Debug protocol, subsystem, SoC-level, and integration failures.
• Validate Wi-Fi and Low Power Wireless functionality.
• Debug RF interface and digital/RF integration issues.
• Develop and run constrained-random verification scenarios.
• Implement and monitor functional coverage and SystemVerilog Assertions (SVA).
• Work closely with RTL Design, Firmware, Architecture, RF, and Validation teams.
• Drive verification issue resolution and closure with focus on quality.
• Support verification activities across the SoC development and validation lifecycle.

Skills

SystemVerilog

UVM

Verification Envs

RTL GLS Debug

Regression Debug

WiFi LPW SoCs

SoC RF interface

Job description

Location: Bangalore
Experience: 6–10 Years
Open Positions: 5

Job Overview

We are looking for experienced Wireless Design Verification Engineers to support the verification of next-generation Wi-Fi and Low Power Wireless (LPW) SoCs .

The role involves developing and maintaining SystemVerilog/UVM-based verification environments , executing RTL and Gate-Level Simulation (GLS) regressions, debugging complex failures, and validating SoC and RF interface functionality.

The ideal candidate should be capable of working independently on UVM-based verification, regression debug, protocol validation, and SoC/RF interface integration .

Key Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments .
• Develop detailed verification plans, test cases, sequences, scoreboards, checkers, and assertions.
• Execute RTL and Gate-Level Simulation (GLS) regressions .
• Analyze regression failures and perform detailed root-cause analysis.
• Debug protocol, subsystem, SoC-level, and integration failures independently.
• Validate Wi-Fi and Low Power Wireless functionality.
• Debug RF interface and digital/RF integration issues.
• Develop and execute constrained-random verification scenarios.
• Implement and monitor functional coverage and SystemVerilog Assertions (SVA) .
• Work closely with RTL Design, Firmware, Architecture, RF, and Validation teams .
• Drive verification issue resolution and closure with a strong focus on quality.
• Support verification activities across the SoC development and validation lifecycle.