Lead Engineer – IC Verification

Silabs India Private Limited

Hyderabad

On-site

INR 3,500,000 - 5,500,000

Full time

13 days ago

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Benefits offered by this job

Equity rewards (RSUs)
Insurance plans with outpatient cover
National Pension Scheme (NPS)
Flexible work policy
Childcare support

Job summary

Silicon Labs in Hyderabad, India is seeking an experienced Design Verification Engineer to verify complex modem baseband and PHY-layer IPs powering Wi‑Fi and IoT devices. You will build SystemVerilog/UVM environments and drive coverage closure across full verification cycles.

Join a team collaborating with RTL designers and system engineers to deliver high-quality wireless SoCs, using advanced methodologies and AI-powered tools to boost productivity and decision-making.

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Electronics, Communication Engineering, or a related field.
  • 7–15 years of experience in RTL Design Verification, preferably involving mixed-signal datapath, modem baseband, or PHY-layer modules.
  • Strong hands-on expertise in SystemVerilog and UVM verification methodologies.
  • Experience developing UVM testbench components such as agents, drivers, monitors, scoreboards, and coverage models.
  • Strong understanding of constrained-random testing, functional coverage, and coverage closure.
  • Experience integrating C-based reference models for bit-exact functional verification.
  • Good understanding of digital communication systems and PHY-layer concepts.
  • Strong debugging, problem-solving, and cross-functional collaboration skills.

Responsibilities

  • Develop and maintain SystemVerilog/UVM-based verification environments for modem digital baseband and PHY-layer IPs.
  • Design and implement module-level and subsystem-level testbenches, including drivers, monitors, agents, scoreboards, and coverage models.
  • Define and execute comprehensive verification plans to ensure functional correctness and design quality.
  • Drive constrained-random verification, functional coverage, and coverage closure.
  • Perform bit-exact verification by integrating C-based algorithmic reference models into verification environments.
  • Verify complex mixed-signal datapath and PHY-layer modules used in wireless communication systems.
  • Debug complex RTL and testbench issues, working closely with design and system engineering teams to identify root causes.
  • Collaborate across functional teams to resolve integration challenges and ensure successful IP verification and delivery.
  • Participate in design reviews, verification planning, and continuous improvement of verification methodologies.

Skills

RTL Verification
SystemVerilog/UVM
Constrained-random testing
Bit-exact verification with C models
Digital baseband/ PHY concepts
Debugging & cross-functional collab
AI-powered verification tools

Education

Bachelor's or Master's in EE/ECE/CE

Tools

SystemVerilog
UVM
C-based reference models

Job description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting‑edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

The Role

In this role, you will work on verifying complex digital RTL blocks within wireless modem baseband and PHY-layer subsystems that power Wi‑Fi and low‑power IoT devices. You will play a key role in ensuring the functional correctness, performance, and reliability of modem IPs used in Silicon Labs' wireless SoCs. This is a great opportunity for an experienced Design Verification Engineer who enjoys solving complex technical challenges, developing robust verification environments, and working closely with design and systems teams to deliver high‑quality wireless solutions.

Meet the Team

Our Modem team develops digital baseband and PHY-layer IPs that enable wireless connectivity across Wi‑Fi and low‑power IoT applications. As part of this team, you will collaborate closely with RTL designers, modem system engineers, verification engineers, and SoC teams to verify complex modem IPs and ensure seamless integration into wireless SoCs.

Responsibilities
  • Develop and maintain SystemVerilog/UVM‑based verification environments for modem digital baseband and PHY‑layer IPs.
  • Design and implement module‑level and subsystem‑level testbenches, including drivers, monitors, agents, scoreboards, and coverage models.
  • Define and execute comprehensive verification plans to ensure functional correctness and design quality.
  • Drive constrained‑random verification, functional coverage, and coverage closure.
  • Perform bit‑exact verification by integrating C‑based algorithmic reference models into verification environments.
  • Verify complex mixed‑signal datapath and PHY‑layer modules used in wireless communication systems.
  • Debug complex RTL and testbench issues, working closely with design and system engineering teams to identify root causes.
  • Collaborate across functional teams to resolve integration challenges and ensure successful IP verification and delivery.
  • Participate in design reviews, verification planning, and continuous improvement of verification methodologies.
Skills
  • Bachelor's or Master's degree in Electrical Engineering, Electronics, Communication Engineering, or a related field.
  • 7–15 years of experience in RTL Design Verification, preferably involving mixed‑signal datapath, modem baseband, or PHY‑layer modules.
  • Strong hands‑on expertise in SystemVerilog and UVM verification methodologies.
  • Experience developing UVM testbench components such as agents, drivers, monitors, scoreboards, and coverage models.
  • Strong understanding of constrained‑random testing, functional coverage, and coverage closure.
  • Experience integrating C‑based reference models for bit‑exact functional verification.
  • Good understanding of digital communication systems and PHY‑layer concepts.
  • Strong debugging, problem‑solving, and cross‑functional collaboration skills.
Skills That Will Make You Stand Out
  • Experience with IEEE 802.11 Wi‑Fi, 4G/5G cellular, or other OFDM‑based communication systems.
  • Hands‑on experience verifying wireless modem baseband and digital signal processing IPs.
  • Knowledge of DSP blocks such as FFT, FIR filters, correlators, and FEC decoders.
  • Experience working with mixed‑signal verification environments and digital/analog interfaces.
  • Experience with subsystem‑level verification and integration of complex IPs into wireless SoCs.
  • Ability to independently own verification activities and drive complex debugging and coverage closure.
  • Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision‑making.
Benefits & Perks
  • Equity Rewards (RSUs)
  • Insurance plans with outpatient cover
  • National Pension Scheme (NPS)
  • Flexible work policy
  • Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job‑related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

At Silicon Labs, we hire and empower great talent to achieve their full potential. By offering challenging projects, technical mentorship, and continuous learning opportunities, we ensure our employees thrive at every stage of their careers. Here, you’ll work alongside some of the industry’s brightest minds, tackling complex problems that deepen your expertise and expand your horizons. Whether you’re building new skills or shaping your career path, we’re dedicated to supporting your growth and celebrating your success every step of the way.

Please note that our Company never asks for personal information unrelated to the job application process, such as bank or credit card data and never charges any fees to apply to any jobs.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Lead Engineer – RTL Design (Wireless Modem IP)
Lead Engineer – RTL Design (Wireless Modem IP)

Silabs India Private Limited • Hyderabad

On-site
INR 4,500,000 - 7,500,000
Equity Rewards (RSUs)
Insurance plans with outpatient cover
National Pension Scheme (NPS)
+2
Lead Engineer – IC Verification
Lead Engineer – IC Verification

Silicon Labs • Hyderabad

On-site
INR 2,800,000 - 5,600,000
Equity Rewards (RSUs)
Insurance plans with outpatient cover
National Pension Scheme (NPS)
+2
Lead Engineer – IC Verification
Lead Engineer – IC Verification

Silicon Labs • Hyderabad

On-site
INR 3,500,000 - 6,500,000
Manager / Senior Manager – Design Verification
Manager / Senior Manager – Design Verification

Silicon Labs GmbH • Hyderabad

On-site
INR 4,000,000 - 7,000,000
Equity RSUs
Insurance (Outpatient)
National Pension Scheme
+2
Staff/Senior Staff Engineer - AMS Verification
Staff/Senior Staff Engineer - AMS Verification

Silabs India Private Limited • Hyderabad

On-site
INR 3,000,000 - 5,400,000
Equity rewards (RSUs)
ESPP
Insurance plans with outpatient cover
+3
Senior Engineer - IC Design (RTL AMS)
Senior Engineer - IC Design (RTL AMS)

Silabs India Private Limited • Hyderabad

Hybrid
INR 1,200,000 - 1,800,000
Equity Rewards (RSUs)
Insurance plans with Outpatient cover
National Pension Scheme (NPS)
+2
Lead RTL Engineer ( Mixed-Signal IPs)
Lead RTL Engineer ( Mixed-Signal IPs)

Silabs India Private Limited • Hyderabad

On-site
INR 2,400,000 - 4,200,000
Equity Rewards (RSUs)
Insurance plans with Outpatient cover
National Pension Scheme (NPS)
+2
Lead Engineer RTL Design Wireless Modem IP
Lead Engineer RTL Design Wireless Modem IP

Silicon Labs • Hyderabad

On-site
INR 3,500,000 - 5,500,000
Equity Rewards (RSUs)
Insurance plans with outpatient cover
National Pension Scheme (NPS)
+2
Lead Engineer – RTL Design (Wireless Modem IP)
Lead Engineer – RTL Design (Wireless Modem IP)

Silicon Labs • Hyderabad

On-site
INR 2,500,000 - 3,500,000
Lead Engineer - SW Design - RAIL
Lead Engineer - SW Design - RAIL

Silicon Labs GmbH • Hyderabad

On-site
INR 3,500,000 - 4,800,000
Equity Rewards (RSUs)
Insurance plans with Outpatient cover
National Pension Scheme (NPS)
+2