PD Engineer - Noida

Tecquire Solutions Pvt Ltd; Dadri; On-site; INR 800,000 - 1,500,000; Full time

Job summary

Tecquire Solutions Pvt Ltd in Dadri, Uttar Pradesh is looking for a professional with a Bachelor's or Master's degree in Electronics/ Electrical Engineering. Candidates should have 2-6 years of experience in digital physical design of SoCs or ASICs. Responsibilities include executing physical design activities, performing verification, and analyzing timing issues. Proficiency in industry-standard EDA tools such as Fusion Compiler, Innovus, and Calibre is essential. A strong ownership mindset and ability to communicate effectively are desired.

Qualifications

• 2-6 years of hands-on experience in digital physical design of SoCs or ASICs.
• Ability to independently drive and close assigned blocks.
• Clear communication of risks and closure status.

Responsibilities

• Execute physical design activities including floor planning, power planning, placement, CTS, routing, and STA.
• Perform physical verification (DRC, LVS, Antenna) and resolve violations.
• Analyze and debug timing, congestion, power, and signal integrity issues.
• Support DFT implementation and ensure proper test structure integration.

Skills

Digital physical design of SoCs or ASICs

Proficiency with EDA tools (Fusion Compiler / Innovus / ICC2, Tempus / PrimeTime, Voltus / RedHawk, Calibre)

Floorplanning and power planning

Placement and routing optimization

Clock tree synthesis (CTS)

Static Timing Analysis (STA)

Physical verification and reliability checks

Education

Bachelor’s or Master’s degree in Electronics / Electrical Engineering or related field

Job description

Responsibilities

• Execute physical design activities including floor planning, power planning, placement, CTS, routing, and STA for assigned blocks
• Perform physical verification (DRC, LVS, Antenna) and resolve violations to achieve clean signoff
• Conduct power integrity analysis (IR drop, EM) and support PDN optimization
• Support DFT implementation and ensure proper test structure integration
• Analyze and debug timing, congestion, power, and signal integrity issues
• Execute ECOs and support tape‑out readiness under tight schedules
• Develop and use automation scripts to improve flow efficiency
• Contribute to methodology improvements and standardization efforts
• Collaborate with team members on implementation strategies, constraints, and floorplans

Qualifications

• Bachelor’s or Master’s degree in Electronics / Electrical Engineering or related field
• 2–6 years of hands‑on experience in digital physical design of SoCs or ASICs
• Proficiency with industry‑standard EDA tools (Fusion Compiler / Innovus / ICC2, Tempus / PrimeTime, Voltus / RedHawk, Calibre)
• Solid understanding of Floorplanning and power planning basics
• Solid understanding of Placement and routing optimization
• Solid understanding of Clock tree synthesis (CTS)
• Solid understanding of Static Timing Analysis (STA) and timing closure techniques
• Solid understanding of Physical verification and reliability checks
• Exposure to advanced nodes (16nm / 7nm / 5nm preferred)

Soft Skills

• Ability to independently drive and close assigned blocks
• Structured debugging approach for timing, IR/EM, and tool‑related issues
• Clear communication of risks and closure status
• Strong ownership mindset and execution discipline