Lead Design for test (DFT) Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd seeks an experienced DFT Engineer to drive end-to-end test architecture and implementation for complex ASIC/SoC designs. You will own DFT strategy across the full chip lifecycle, collaborating with design, verification, and physical teams to ensure high test coverage and quality.

You will implement DFT architecture, perform scan insertion, ATPG, compression, fault grading, and develop DFT specs.

Qualifications

• 7 to 14 years of hands-on DFT experience.
• Strong architecture and execution skills across full chip lifecycle.
• Experience with scan, ATPG, and BIST techniques.

Responsibilities

• Define and implement DFT architecture for large SoCs/ASICs.
• Own end-to-end DFT strategy including Scan, ATPG, MBIST/LBIST, and Boundary Scan.
• Perform scan insertion, ATPG pattern generation, compression, and fault grading.
• Develop and maintain DFT specifications and ensure design-cycle compliance.
• Integrate DFT logic at RTL and gate-level; collaborate with verification for pattern simulation.
• Work with physical design to meet timing, power, and area constraints.
• Debug silicon bring-up issues and support ATE test pattern validation.
• Mentor junior engineers and drive improvements in DFT methodologies and flows.

Skills

DFT architecture

ATPG

MBIST/LBIST

JTAG/Boundary Scan

DFT tools

RTL/GLS familiarity

pattern simulation

debugging and problem solving

leadership and mentoring

cross-functional collaboration

Tools

Synopsys DFT Compiler

Tetramax

Tessent

Job description

We are looking for experienced DFT Engineers to drive end-to-end test architecture and implementation for complex ASIC/SoC designs.

Experience: 7 to 14yrs

In this role, you will own and drive Design for Test (DFT) strategy, architecture, and implementation across the full chip lifecycle. You will work closely with design, verification, physical design, and silicon validation teams to ensure high product quality and test coverage.

• Define and implement DFT architecture for large, complex SoCs/ASICs
• Own end-to-end DFT strategy and execution including Scan, ATPG, MBIST, LBIST, JTAG, and Boundary Scan
• Perform Scan insertion, ATPG pattern generation, compression, and fault grading
• Develop and maintain DFT specifications and ensure compliance throughout the design cycle
• Integrate and verify DFT logic at RTL and gate-level (GLS)
• Collaborate with verification teams for pattern simulation, validation, and debug
• Work closely with physical design teams to meet timing, power, and area constraints
• Debug silicon bring-up issues and support ATE test pattern validation
• Drive improvements in DFT methodologies and flows
• Mentor junior engineers and provide technical leadership
• Strong expertise in Scan, ATPG, BIST (MBIST/LBIST), JTAG/Boundary Scan, and compression techniques
• Hands-on experience with DFT tools such as Synopsys DFT Compiler, Tetramax, Tessent, or equivalent
• Solid understanding of RTL design, synthesis, and verification flows
• Familiarity with STA and physical design constraints related to DFT
• Experience in silicon bring-up and ATE test pattern generation
• Strong debugging and analytical skills
• Proven ability to own and drive DFT closure for complex chips
• Strong collaboration across cross-functional teams
• Leadership mindset with mentoring capabilities
• Excellent communication and problem-solving skills