DFT Engineer

Wissen Infotech; Bengaluru; Hybrid; INR 300,000 - 600,000; Full time

Job summary

Wissen Infotech seeks an experienced DFT Staff Engineer to drive Design-for-Test (DFT) architecture, implementation, verification, and silicon bring-up for complex SoCs and IPs. You will define and implement DFT architecture for IP, subsystem, and SoC-level designs, and develop test methodologies including Scan, ATPG, MBIST/LBIST, Boundary Scan, and Test Compression.

The role requires balancing test coverage with silicon area, power, performance, and cost while integrating testability early in

Qualifications

• Experience in DFT architecture and implementation for SoCs.
• Strong knowledge of scan chain design, ATPG, MBIST/LBIST.
• Experience with DFT bring-up and verification.

Responsibilities

• Define and implement DFT architecture for IP, subsystem, and SoC-level designs.
• Develop and deploy test methodologies including Scan, ATPG, MBIST, LBIST, Boundary Scan, and Test Compression.
• Integrate testability requirements early in the RTL design cycle.
• Drive DFT strategy balancing test coverage, silicon area, power, performance, and test cost.

Skills

DFT

ATPG

MBIST/LBIST

Boundary Scan

STA

RTL DFT

Test Methodologies

Tools

JTAG

ATPG Tools

MBIST Tools

Boundary Scan Tools

Job description

We are seeking an experienced DFT Staff Engineer to drive Design-for-Test (DFT) architecture, implementation, verification, and silicon bring-up activities for complex SoCs and IPs. The ideal candidate will have strong expertise in scan, ATPG, MBIST/LBIST, boundary scan, STA, and end-to-end DFT execution, ensuring high-quality, testable, and manufacturable semiconductor products.

• Define and implement DFT architecture for IP, subsystem, and SoC-level designs.
• Develop and deploy test methodologies including Scan, ATPG, MBIST, LBIST, Boundary Scan (JTAG), and Test Compression.
• Integrate testability requirements early in the RTL design cycle.
• Drive DFT strategy while balancing test coverage, silicon area, power, performance, and test cost.