Technical Director – DFT

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 1,800,000 - 3,500,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru seeks a Technical Director – DFT to lead architecture and execution of DFT solutions for complex high-performance SoCs. You will own the technical strategy and guide the DFT methodology across multiple IPs.

The role requires deep expertise across DFT architecture, ATPG, memory test, scan, test compression and DFT sign-off, with leadership to mentor engineers and drive sign-off readiness for complex silicon programs.

Qualifications

• 16–25 years of hands-on ASIC/SoC DFT experience.
• Deep expertise in DFT architecture, ATPG, MBIST and Test Compression.
• Experience with Synopsys/Mentor DFT tools.

Responsibilities

• Define and drive DFT architecture and methodology.
• Lead DFT implementation across SoCs including IPs and hierarchies.
• Own end-to-end DFT flow from architecture to sign-off.
• Mentor engineers and establish DFT standards.
• Evaluate emerging DFT technologies for next-gen designs.

Skills

DFT architecture

ATPG

MBIST

LBIST

Test Compression

DFT sign-off

RTL collaboration

Scripting TCL/Perl/Python

SoC test methodology

Education

B.E./B.Tech/M.Tech in Electronics/Electrical Engineering/VLSI

Tools

Synopsys TestMAX/TetraMAX

Mentor Tessent

Job description

We are looking for a Technical Director – DFT to lead the architecture and execution of DFT solutions for complex, high-performance SoCs. The role requires deep expertise across DFT architecture, ATPG, memory test, scan, test compression and DFT sign-off, with strong ownership of technical strategy and methodology.

Key Responsibilities

• Define and drive DFT architecture and methodology for complex SoCs across multiple IPs and hierarchical designs.
• Lead Scan, ATPG, MBIST, LBIST, JTAG, Boundary Scan, EDT, Test Compression and OCC implementation.
• Own DFT flow from architecture/specification through implementation, ATPG, verification and sign-off.
• Drive fault coverage, pattern quality, test time and test-power optimization.
• Resolve complex issues involving ATPG, scan chains, compression, clocking, timing and DFT rule violations.
• Define strategies for hierarchical DFT, block-level integration and SoC-level test architecture.
• Drive DFT implementation for advanced-node and high-complexity SoC designs.
• Partner closely with RTL, Design Verification, Physical Design, STA, Silicon Validation and Product Engineering teams.
• Develop scalable DFT methodologies, automation frameworks and reusable flows.
• Provide technical leadership for DFT sign-off, tape-out readiness and post-silicon debug.
• Evaluate and adopt emerging DFT technologies and methodologies for next-generation SoCs.
• Mentor senior engineers and establish strong technical standards across DFT teams.
• Lead technical reviews, architecture discussions and resolution of critical DFT escalations.

Required Expertise

• 16–25 years of hands-on experience in ASIC/SoC DFT.
• Deep expertise in DFT architecture, Scan, ATPG, MBIST and Test Compression.
• Strong knowledge of Synopsys TestMAX/TetraMAX, Mentor Tessent or equivalent DFT tools.
• Strong understanding of SoC architecture, clocking, timing, power and physical implementation constraints.
• Proficiency in TCL/Perl/Python for DFT automation and flow development.
• Experience with advanced process nodes and large-scale SoC programs.
• Strong understanding of DFT verification, ATPG simulation, coverage analysis and silicon correlation.
• Excellent technical communication, architecture and problem-solving skills.
• B.E./B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI or related discipline.