Verification Lead

Mulya Technologies; Hyderabad; On-site; INR 2,500,000 - 5,000,000; Full time

Job summary

Mulya Technologies in India is seeking a DV lead with 11+ years of hands-on DV experience in System Verilog/UVM to own and drive the verification of a block, subsystem, or SoC.

You will lead a team of engineers, execute test plans, develop testbenches, and hit coverage goals on time. Expertise in IP/sub-system or SoC level verification using SV/UVM is essential, with exposure to gatesims and debug across the verification flow.

Qualifications

• 11+ years of hands-on DV experience in System Verilog/UVM.
• Ability to own and drive verification of a block/subsystem or SOC.
• Proven track record of leading a team of engineers.
• Extensive experience in IP/sub-system and/or SoC level verification using SV/UVM.
• Experience in test plan and testbench development and constrained random UVM tests.
• Execution of test plans to hit coverage goals on time.
• Strong debugging across the verification flow including Gatesims.
• Experience in PCIe/UCIe, CXL/NVMe, AXI/ACE/CHI, Ethernet/RDMA, DDR/LPDDR/HBM, ARM/RISC-V.
• Power aware simulations with UPF; scripting is a plus.
• Experience with SV/UVM verification tools and RTL troubleshooting.

Responsibilities

• Own and drive verification of a block/subsystem or SOC.
• Lead a team of engineers in DV activities.
• Develop test plans and testbenches to achieve coverage goals.
• Execute constrained random UVM tests and debug across flows.
• Collaborate across DV teams and integrate IP/SOC verification.

Skills

SystemVerilog/UVM

Block/Subsystem/SoC verification

Team leadership

Test plan and testbench development

Constrained random UVM tests

Debugging across verification flow

Gatesims experience

Power Aware Simulations UPF

SV/UVM verification in IP/SoC

SVA and formal verification (desirable

Python/Perl/TCL scripting (desirable)

Tools

VCS

Verdi

Cadence Xcelium

Simvision

Jasper

Git

Perforce

Clearcase

Job description

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

DV lead:

• 11+ years of hands-on DV experience in System Verilog/UVM.
• Must be able to own and drive the verification of a block / subsystem or a SOC.
• Should have a track record of leading a team of engineers.
• Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.
• Experience in Test plan and Testbench development,
• Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.
• Should be good with debugging and exposed to all aspects of verification flow including Gatesims
• Must have extensive experience in verification of one or more of the following:
• PCI Express or UCIe, CXL or NVMe
• AXI, ACE or CHI
• Ethernet, RoCE or RDMA
• DDR or LPDDR or HBM
• ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages
• Power Aware Simulations using UPF
• Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper.
• Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase.
• Experience in SVA and formal verification is desirable (not a must)
• Script development using Python, Perl or TCL is desirable (not a must)