Verification Lead

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Mulya Technologies in Bengaluru is seeking a senior DV verification lead with 11+ years in SystemVerilog/UVM to own verification for blocks or SOCs. You will drive testbench development, constrained-random testing, and coverage goals while leading a team of engineers through the DV flow, gatesims, and debugging across IP/sub-system verification.

The role requires hands-on experience with SV/UVM, test plans, and strong debugging skills, plus familiarity with common DV toolchains and version

Qualifications

• 11+ years of hands-on DV experience in SystemVerilog/UVM.
• Led verification for a block/subsystem or SOC and team.
• Experience in test plan and testbench development with constrained random tests.
• Debugging across the full verification flow, gatesims included.
• Experience with PCIe/UCIe, AXI/CH, Ethernet/RDMA, DDR/LDDR/HBM, ARM/RISC-V subsystems.

Responsibilities

• Own and drive the verification of a block, subsystem or SOC.
• Lead a team of engineers to meet schedule and quality targets.
• Develop and execute test plans and coverage strategies.
• Debug across DV flow and verify IP/sub-system requirements.

Skills

SystemVerilog

UVM

DV verification

Testbench development

Constrained random testing

C/Assembly for CPU subsystems

Gatesims debugging

Power Aware Simulations UPF

SVA / formal verification

Python scripting

Version control (Git etc.)

Tools

VCS

Verdi

Cadence Xcelium

Simvision

Jasper

Git

Perforce

Clearcase

Job description

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

DV lead

• 11+ years of hands-on DV experience in System Verilog/UVM.
• Must be able to own and drive the verification of a block / subsystem or a SOC.
• Should have a track record of leading a team of engineers.
• Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.
• Experience in Test plan and Testbench development,
• Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.
• Should be good with debugging and exposed to all aspects of verification flow including Gatesims
• Must have extensive experience in verification of one or more of the following:
• PCI Express or UCIe, CXL or NVMe
• AXI, ACE or CHI
• Ethernet, RoCE or RDMA
• DDR or LPDDR or HBM
• ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages
• Power Aware Simulations using UPF
• Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper.
• Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase.
• Experience in SVA and formal verification is desirable (not a must)
• Script development using Python, Perl or TCL is desirable (not a must)