Lead Verification Engineer

ACL Digital; Pune District; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

ACL Digital seeks a Senior Design Verification Engineer in Pune to lead a 56-member DV team, driving full ASIC/SoC verification from concept to tape-out. You will design verification plans, TBs, and portable infrastructure, and build reusable SystemVerilog/UVM environments with multi-instance VIPs.

Strong PCIe/Ethernet/USB/AMBA skills are required. You will collaborate across Design, SW/FW, and Architecture to ensure coverage and successful tape-out, with 8+ years DV experience and leadership

Qualifications

• BS/ MS in EE/CS; 8+ years total DV experience; 2+ years leading complex IP verification.

Responsibilities

• Lead a 56-member DV team while driving full ASIC/SoC verification from concept to tape-out.
• Create IP and sub-system verification plans, testbenches (TB), sequences, and portable verification infrastructure.
• Build reusable SystemVerilog/UVM environments; integrate multi-instance VIPs at the SoC level.
• Hands-on experience verifying PCIe, Ethernet, USB, and AMBA bus architectures.
• Expertise in UPF integration, boot-up, power-cycling, and firmware/hardware interaction verification.
• Collaborate with Design, SW/FW, and Architecture teams to hit coverage targets.

Skills

Leadership

Architecture & Planning

UVM Integration

High-Speed & Bus Protocols

Low-Power HW/FW

Cross-Functional Ownership

Education

BS/MS in EE/CS

Tools

SystemVerilog/UVM

Job description

Senior Design Verification Engineer (7 -18 Years)

Location: Pune | Notice Period: 45-60 days (Serving notice period only)

Responsibilities & Requirements

• Leadership: Lead a 56 member DV team while driving full ASIC/SoC verification from concept to tape-out.
• Architecture & Planning: Create IP and sub-system verification plans, testbenches (TB), sequences, and portable verification infrastructure.
• UVM Integration: Build reusable SystemVerilog/UVM environments; integrate multi-instance VIPs at the SoC level.
• High-Speed & Bus Protocols: Hands-on experience verifying PCIe, Ethernet, USB, and AMBA bus architectures.
• Low-Power & HW/FW: Expertise in UPF integration, boot-up, power-cycling, and verifying firmware/hardware interactions.
• Cross-Functional Ownership: Collaborate with Design, SW/FW, and Architecture teams to hit coverage targets and ensure tape-out readiness.
• Qualifications: BS/MS in EE/CS; 8+ years total DV experience with 2+ years leading complex IP verification.