DV IP Lead

Quest Global; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Quest Global in Bengaluru seeks an experienced IP DV Lead to focus on functional verification for specific IP blocks. The role involves creating comprehensive test plans and developing UVM environments to ensure complete functional coverage.

Applicants should have over 8 years of experience, strong knowledge in advanced SystemVerilog/UVM, and scripting skills in Python or Perl. Join a dynamic team and contribute to cutting-edge technology in a collaborative environment.

Qualifications

• 8+ years in IP-level functional verification.
• Specific knowledge of USB, Ethernet, or AI accelerators.
• Proficiency in automated testbench scripting.

Responsibilities

• Create comprehensive test plans for functional coverage.
• Build UVM environments including agents and monitors.
• Apply formal methods for complex state machine verification.
• Identify corner-case bugs through functional coverage.
• Maintain high-efficiency regression suites.
• Collaborate with RTL designers to resolve ambiguities.

Skills

Advanced SystemVerilog/UVM

Writing complex SVA

Constrained Random Verification (CRV)

Python or Perl

Job description

Job Requirements

The IP DV Lead is a deep-diver. This role focuses on exhaustive verification of a specific functional block (e.g., a Crypto engine, Video Codec, or High-Speed Controller), ensuring 100% functional and code coverage within that domain.

Core Responsibilities

• Block-Level Strategy: Create comprehensive testplans based on IP functional specifications to reach 100% functional coverage.
• Environment Development: Build highly constrained-random UVM environments, including agents, monitors, and complex scoreboards.
• Formal Verification: Apply formal methods (SVA) to verify complex state machines or data paths where simulation falls short.
• Bug Hunting: Identify corner-case bugs through assertions and functional coverage-driven stimulus.
• Regression Management: Maintain high-efficiency regression suites and lead the closure of code, functional, and toggle coverage.
• Collaboration: Work closely with RTL designers to resolve architectural ambiguities and debug RTL failures.

Required Skills & Qualifications

• Experience: 8+ years in IP-level functional verification.
• Technical Mastery: Advanced SystemVerilog/UVM and expertise in writing complex SVA (SystemVerilog Assertions).
• Domain Expertise: Specific knowledge of the IP being verified (e.g., USB, Ethernet, or AI accelerators).
• Methodology: Strong background in Constrained Random Verification (CRV) and coverage-driven sign-off.
• Scripting: Proficiency in Python or Perl for testbench automation and log parsing.