Verification Engineer – 2+ years

Alpha-Numero; Ahmedabad District; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Alpha-Numero is seeking a Verification Engineer to work across Ahmedabad, Hyderabad and Bangalore, bringing 2+ years of ASIC/FPGA verification experience. You will contribute to robust test plans, SV/UVM based environments, and coverage-driven verification to ensure specifications are thoroughly validated.

The role offers exposure to complex verification challenges, strong problem-solving requirements, and collaboration within a dynamic team in a multi-location setting.

Qualifications

• 2+ years of relevant experience in ASIC/FPGA verification.
• Strong understanding of verification concepts; develop test plans that fully verify requirements/specifications.
• Hands-on experience with SV/UVM based verification environments (agents/UVCs, scoreboards, predictors).
• Experience with constrained-random stimulus, coverage-driven verification, and debugging coverage gaps.
• Excellent problem-solving and debug skills; strong communication abilities.

Skills

ASIC/FPGA verification

Test plan development

SV/UVM verification env

Constrained random tests

Debugging & problem solving

Functional coverage

Code coverage activities

Tools

SV

UVM

Scoreboards

Reference models

GNU make

Python

Perl

Job description

Role:

Verification Engineer

Locations:

Ahmedabad, Hyderabad, Bangalore

No. of positions:

Multiple

Experience

2+ years, Trained Freshers are also welcome

Requirements

• Good industry experience in ASIC/FPGA verification.


• Required to have sound verification concept of developing test plan/test verification that can verify the requirements/specifications completely and robustly


• Required to have working experience in developing SV + UVM based verification env components (such as agents/UVCs, scoreboards, predictors/reference models) and writing tests using constrain random based test sequences.


• Excellent problem-solving skills.


• Required to have experience in implementing functional coverage, debugging the coverage gaps, and writing tests for coverage


• Required to have exposure on code coverage related activities

Value Addition

• Recommended to have working experience of FPGA verification compliance to DO-254 standards. Candidate should have experience in dealing with various DO-254 processes during the life cycle of the project


• Hands on knowledge in scripting language such as GNU make, perl and python


• Recommended to have exposure of verifying DSP blocks such as filters, adders, multipliers limiters using fixed point operations


• Ability to work as individual contributor as well as a team player.


• Excellent verbal and written communication skills