Senior Verification Engineer

Einfochips; Hyderabad, Pune District, Bengaluru; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

Einfochips seeks an experienced ASIC/SoC Verification engineer in Hyderabad to lead verification efforts for SOC/IP/blocks. You will develop testplans, create testbenches and verification environments, and build scoreboards in UVM while ensuring RTL/testbench issues are resolved efficiently.

The role requires deep knowledge of SystemVerilog, UVM, and industry protocols such as Ethernet, PCIe, MIPI, USB, or AMBA.

Qualifications

• 5 to 15 years of experience in SOC/IP/block level functional verification using SystemVerilog/UVM.
• Strong knowledge of UVM and SystemVerilog.
• Experience developing test plans, testbenches, verification environments, and scoreboard in UVM.
• Knowledge of industry standard protocols (Ethernet, PCIe, MIPI, USB, AMBA) is required.
• Proficient at debugging RTL and testbench issues and closing coverage and bugs.

Responsibilities

• Lead a team of 4–5 engineers and coordinate verification activities.
• Develop and maintain testplans, testbenches, and verification environments.
• Design interface agents and scoreboards in UVM and verify IP/SoC blocks.
• Handle runtime project changes and adapt schedules to client needs.

Skills

SOC/IP/Block level verification

SystemVerilog

UVM

RTL debugging

Education

BE/BTech in VLSI/Electronics/Electrical/Computer/Instrumentation

Job description

Asic/SocVerification

5 to 15 years of experience in SOC/IP/block level functionalverificationusing System Verilog/UVM.

Strong knowledge of UVM, advance UVM,System Verilog.

Must have worked on development of testplan, testbench components, verificationenvironment, interface agents, Scoreboard in UVM.

Understanding of complete functionalverificationcycle will be added advantage

Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required.

Skills to debug RTL & testbench issues, test failures.

Experience on verificationclosure by closing Coverage and bug reports

Primarily knowledge of Script development and maintenance

Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc

MUST Be willing to Lead a Team of min 4-5 Engineers.

Must be willing to work from Hyderabad office or customer location as per project demands

EDUCATION BACKGROUND

B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.