Turing - Design Verification - Principal Engineer

Qualcomm; Bengaluru; On-site; INR 400,000 - 700,000; Full time

Job summary

Qualcomm in Bengaluru is seeking an experienced Principal Engineer – Design Verification to join our growing team. You will work on cutting-edge semiconductor technologies and contribute to complex SoC/IP verification initiatives.

Lead verification strategies using SystemVerilog/UVM, apply formal verification with Jasper or VC Formal, and leverage UPF/CPF/PtPx methodologies while mentoring engineers and staying hands-on in execution.

Qualifications

• Strong expertise in Functional Verification, Power-Aware Verification, Formal Verification, and Performance Verification.
• Hands-on experience with UVM and SystemVerilog.
• Knowledge of Jasper or VC Formal for formal verification.
• Understanding of UPF/CPF and PtPx methodologies.

Responsibilities

• This role is ideal for seasoned verification professionals who are passionate about solving complex technical challenges and mentoring engineering teams while remaining deeply involved in execution.

Skills

Functional Verification

Power-Aware Verification

Formal Verification

Performance Verification

Tools

UVM

SystemVerilog

Jasper

VC Formal

UPF/CPF

PtPx

Job description

We are looking for an experienced Principal Engineer – Design Verification to join our growing team in Bangalore. This is an excellent opportunity to work on cutting-edge semiconductor technologies and contribute to complex SoC/IP verification initiatives.

Key Requirements.

• Strong expertise in Functional Verification, Power-Aware Verification, Formal Verification, and Performance Verification
• Deep hands-on experience with UVM and SystemVerilog
• Strong knowledge of Jasper or VC Formal for formal verification
• Good understanding of UPF/CPF and PtPx methodologies

This role is ideal for seasoned verification professionals who are passionate about solving complex technical challenges and mentoring engineering teams while remaining deeply involved in execution.