Senior Design Verification Engineer - Chennai

n Human Resources & Management Systems [ nHRMS ]; Chennai District; On-site; INR 400,000 - 650,000; Full time

Job summary

n Human Resources & Management Systems [ nHRMS ] is seeking a Senior Design Verification Engineer to own functional verification for design blocks and subsystems. You will build verification environments, drive coverage closure, and ensure silicon-quality signoff before tapeout.

The role requires hands-on experience with UVM/SystemVerilog, coverage-driven verification, and toolchains like VCS or Questa. You will lead a small team of verification engineers and collaborate with design, DFT, and

Qualifications

• 5+ years of hands-on experience in functional verification using UVM/SystemVerilog.
• Strong understanding of coverage-driven verification methodology.
• Experience with simulation, debug, and regression tools (VCS/Questa or equivalent).

Responsibilities

• Develop and maintain UVM-based verification environments and testbenches
• Write test plans, directed and constrained-random tests, and functional/code coverage models
• Debug RTL and testbench issues, and drive bugs to closure with design teams
• Perform assertion-based verification (SVA) and formal verification where applicable
• Lead and mentor a team of 3-4 verification engineers
• Own verification signoff and regression health for assigned blocks
• Collaborate with design, DFT, and architecture teams on verification strategy

Skills

UVM/SystemVerilog

Coverage-driven verification

Simulation/Debug/Regression tools

Tools

VCS

Questa

Job description

Job Description:

We are hiring a Senior Design Verification Engineer to own functional verification for design blocks and subsystems. You will build and maintain verification environments, drive coverage closure, and ensure silicon-quality signoff before tapeout.

Key Responsibilities:

• Develop and maintain UVM-based verification environments and testbenches
• Write test plans, directed and constrained-random tests, and functional/code coverage models
• Debug RTL and testbench issues, and drive bugs to closure with design teams
• Perform assertion-based verification (SVA) and formal verification where applicable
• Lead and mentor a team of 3-4 verification engineers
• Own verification signoff and regression health for assigned blocks
• Collaborate with design, DFT, and architecture teams on verification strategy

Requirements:

• 5+ years of hands-on experience in functional verification using UVM/SystemVerilog
• Strong understanding of coverage-driven verification methodology
• Experience with simulation, debug, and regression tools (VCS/Questa or equivalent)