SoC Design Director

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 5,400,000; Full time

Job summary

Mulya Technologies is seeking a Digital Design professional with deep expertise in high‑performance controller and bridge design, micro‑architecture, RTL implementation, and IP integration to advance cutting‑edge connectivity solutions.

You will own block‑level and full‑chip designs from architecture to GDS, ensure timing closure, and support pre‑ and post‑silicon debug while working with Synopsys/Cadence tools and UVM‑based verification.

Qualifications

• Bachelor’s in Electronics/Electrical engineering; Master’s preferred.
• 20+ years of digital design experience focusing on processor, peripherals and full‑chip implementation.
• Proven RTL development, synthesis, and timing closure expertise.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic with ability to handle multiple tasks; proactive, customer‑focused attitude.

Responsibilities

• Design and implement high‑performance digital solutions, including RTL development and synthesis.
• Collaborate with cross‑functional teams on IP integration for processor IPs and peripherals.
• Oversee timing closure, pre‑ and post‑silicon debug, and ensure first‑pass silicon success.
• Utilize Synopsys/Cadence tools and apply UVM‑based verification flows.
• Lead block‑level and full‑chip designs from architecture to GDS with 16nm or below.

Skills

RTL development

timing closure

UVM-based verification

SystemVerilog/Verilog

Python/Perl scripting

Processor IP/ASIC design

PCIe experience

front-end design

gate-level simulations

ARM/ARC processor IP

Education

Bachelor’s in Electronics/Electrical engineering

Master’s degree (preferred)

Tools

Synopsys tools

Cadence tools

Job description

Top30 Semiconductor Organization in the world

Role Overview

We are seeking a Digital Design professional with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solution's.

Key Responsibilities

• Design and implement high-performance digital solutions, including RTL development and synthesis.Collaborate with cross-functional teams on IP integration for processor IPs and peripherals
• Deep knowledge of processor boot process and peripheral implementation with boot firmware inmind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤16nm.Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows
• Basic Qualifications / Experience Level
• Bachelor’s in Electronics/Electrical engineering (Master's prefe rred).Minimum 20+ years of digital design experience, with focus on processor, peripherals and full chip implementation.Proven expertise in RTL development, synthesis, and timing closure.Experience with front-end design, gate-level simulations, and design verification.Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused atttude.

Required Expertise

Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced

nodes (Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O

cycles .Hands-on experience with processor IP (

ARM/ARC)

Experience of working on PCIe is a must

.Hands-on pre-silicon and post-silicon implementing peripherals for I2C/

SPI/UART

Hands-on experience with complex DMA engines and FW interaction

.Strong proficiency in System Verilog/Verilog and scripting (Python/Perl)

.Experience with block-level and full-chip design at advanced nodes (≤ 16nm)

.Silicon bring-up and post-silicon debug experience

.Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification

.Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Preferred Experience

• Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation

is a plus

.Knowledge of system-level design with ARM/ARC/RISC-V processorssub systems

Experience of working on PCIe/UAL isa big plus

.Understanding of PAD design, DFT, and floor planning

.Experience in synthesis, and timing closure is a big plus

.Experience with NIC, switch, or storage product development

.Familiarity with working in design and verification workflows in a CI/CD environment.

Skils