System-on-Chip Design Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 800,000 - 1,800,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru, India is seeking a System-on-Chip (SoC) Design Engineer with 5–12 years of ASIC/SoC RTL experience to design high-performance subsystems.

You will collaborate with architecture, verification, DFT, and physical design teams to deliver PPA-optimized RTL for next-generation AI, Compute, and Networking SoCs; on-site role in an advanced semiconductor environment.

Qualifications

• 5-12 years of ASIC/SoC RTL design experience.
• Strong microarchitecture and RTL design expertise.
• Proficiency in Verilog/SystemVerilog and ARM-based SoC architecture.
• Experience with AMBA protocols, high-speed interfaces, and Synopsys Design Compiler.
• Hands-on with Lint, CDC/RDC, VCS/Xcelium/Questa, and Python/Tcl/Perl scripting.
• Exposure to advanced nodes (7nm/5nm/3nm) is a plus.

Responsibilities

• Design microarchitecture and RTL for SoC IPs and full subsystems.
• Integrate AMBA interconnects and IPs across architecture, verification, and synthesis.
• Optimize for Power, Performance, and Area (PPA) and ensure timing closure.
• Support silicon bring-up and debug with tooling.
• Collaborate with cross-functional teams to deliver production-ready RTL.

Skills

ASIC RTL design

RTL Design

Verilog SystemVerilog

ARM-based SoC

AMBA protocols

High-speed interfaces

Design Compiler

Lint

CDC RDC

Python Tcl Perl scripting

Tools

Synopsys Design Compiler

VCS/Xcelium/Questa

Job description

Job Description:

About This Job

LeadSoc Technologies Pvt Ltd

Location:

Bengaluru, Karnataka, India

Work Mode:

On-site

Industry:

Semiconductor Manufacturing,IT Services and IT Consulting,Engineering Services

Job Description

System-on-Chip (SoC) Design Engineer

Location: Bengaluru, India

Experience: 5-12 Years

Role

Design and implement high-performance SoC subsystems from microarchitecture to silicon. Collaborate with architecture, verification, DFT, STA, and physical design teams to deliver high-quality, PPA-optimized RTL for next-generation AI, Compute, and Networking SoCs.

Responsibilities

Develop microarchitecture and RTL using Verilog/SystemVerilog.Design datapaths, pipelines, FSMs, memory interfaces, and control logic.Integrate SoC IPs and AMBA-based interconnects (AXI/AHB/APB).Optimize designs for Power, Performance, and Area (PPA).Drive RTL quality through Lint, CDC/RDC, synthesis, and debug.Support timing closure, verification, and silicon bring-up.

Required Skills

5-12 years of ASIC/SoC RTL Design experience.Strong microarchitecture and RTL design expertise.Proficiency in Verilog/SystemVerilog and ARM-based SoC architecture.Experience with AMBA protocols, high-speed interfaces, and Synopsys Design Compiler.Hands-on with Lint, CDC/RDC, VCS/Xcelium/Questa, and Python/Tcl/Perl scripting.Exposure to advanced nodes (7nm/5nm/3nm) is a plus.