Synthesis Lead

Mirafra; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Mirafra is seeking an experienced ASIC Design professional in Bengaluru to drive design flow, perform synthesis and timing closure, and collaborate with design and physical teams on floorplanning and timing reviews.

The role requires 7+ years in ASIC/SoC/Full-chip contexts, proficiency with Synopsys DC/PT and Verilog/VHDL, and familiarity with sign-off methodologies and memory models.

Qualifications

• Experience in ASIC design flow and tape-out readiness.
• Hands-on synthesis and static timing analysis.
• Proficiency with Synopsys DC & PT tools; Verilog/VHDL is a must.
• Desirable scripting in Perl, TCL and shell.
• Ability to work independently with strong analytical skills.
• Work with preplacement/ timing constraints and floorplanning.
• Familiar with physical verification (LVS/ERC/PERC, DFM, OPC).
• Experience with sign-off methodology and timing reviews.

Responsibilities

• Work with design team to derive preplacement requirements and timing constraints.
• Collaborate with physical design for floorplanning, placement and timing reviews.
• Develop sign-off methodology and support a larger team.
• Review standard cell profiles, timing models and memory models.
• Perform physical verification (LVS, ERC/PERC, DFM, OPC) at block or full-chip level.

Skills

ASIC design flow

Synthesis

Static Timing Analysis

Verilog

VHDL

Interpersonal skills

Independent work

Timing constraints

Floorplanning

Placement & timing reviews

Memory models

Physical verification

LVS/ERC

Education

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Tools

Synopsys DC

Synopsys PT

Cadence Genus

DCG/NXT/FC

Verilog

VHDL

Perl

TCL

Shell scripting

Job description

• Good understanding of ASIC design flow.
• Hands on experience in synthesis and static timing analysis.
• Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must.
• Experience in Perl, TCL and shell scripting is desirable.
• Excellent interpersonal & analytical skills with ability to work independently.
• Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus).
• Constraints development, Formal Verification, CECO, Static Timing Analysis & timing closure.
• Work closely with design team to come up with preplacement requirements & timing constraints.
• Work closely with physical design team for floorplan, placement & timing reviews.
• Work closely with cross-functional teams to review standard cell profile, timing models & memory models.
• Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-level.
• Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries.
• Experience in developing sign-off methodology/flow to and supporting a larger team

Experience (years) : 7+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent