Senior Synthesis Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd is seeking a Senior Synthesis Engineer (VLSI) to drive advanced physical synthesis for 7nm/5nm and future sub-micron technologies. You will work hands-on with Fusion Compiler or Genus to meet multi-corner, multi-mode, low-power, performance and area goals.

Responsibilities include logic equivalence checks, pre-STA timing analysis using Primetime/Tempus, low-power checks with Conformal Low Power or VCLP, DFT insertion, and collaboration with RTL, DFT and PD teams to

Qualifications

• 7nm/5nm or future sub-micron technologies experience.

Responsibilities

• Hands-on with Fusion Compiler or Genus for Synthesis tasks.
• Debug and optimize timing and power with Conformal tools.
• Co-work with RTL, DFT and PD engineers to meet PPA targets.
• Develop TCL/Perl/Shell scripts to automate flows.
• Verify constraints quality and completeness.
• Understand UPF & low power concepts and ensure robust implementations.

Skills

Physical Synthesis

Logic Equivalence Check

Pre-STA timing analysis

Low Power check debugging

UPF & Low Power concepts

DFT concepts

TCL/Perl/Shell scripting

Cross-functional collaboration

Debugging/problem solving

Synthesis experience

Tools

Fusion Compiler

Genus

Conformal LEC

Formality

Primetime

Tempus

Conformal Low Power

Job description

Job Description – Senior Synthesis Engineer (VLSI)

• Worked on 7nm/5nm/Future sub-micron Technologies.
• Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus.
• Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or Formality.
• Familiar with pre-STA timing analysis using Primetime or Tempus.
• Familiar with low power check using Conformal Low Power or VCLP tool.
• Experience in verifying constraints quality and completeness.
• Understanding of UPF & Low power concepts.
• Familiar with functional ECO flow and implementation.
• Familiar with DFT Insertion and debugging basic DFT issues.
• Co-work with RTL, DFT and PD engineers to meet PPA targets.
• Well versed with TCL/Perl/Shell script.
• Self-starter and highly motivated.
• Strong debugging, initiative and analysis/problem solving skills.
• Minimum 3+ years of experience in Synthesis and Physical Synthesis