Sr Synthesis and Implementation Engineer

NXP Semiconductors; Dadri; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

NXP Semiconductors is looking for a highly motivated Synthesis & Front-End Implementation Engineer to join our dynamic AI NPU team in Dadri, Uttar Pradesh, India. You will be critical in translating RTL designs into optimized gate-level netlists while ensuring performance, power, and area targets for complex IP blocks.

Ideal candidates will possess a Bachelor's or Master's degree in VLSI or Electronics Engineering with over 5 years of experience in digital ASIC/SoC design. The position involves collaboration with various engineering teams and focuses on logical and physical synthesis of RTL designs.

Qualifications

• 5+ years of relevant experience in digital ASIC/SoC design.
• Experience with physical synthesis and floorplanning aspects.
• Understanding of UPF, low-power design techniques.

Responsibilities

• Perform logical and physical synthesis of RTL designs.
• Develop and implement robust timing constraints.
• Conduct STA and collaborate for timing closure.
• Execute formal verification to ensure functional equivalency.
• Analyze and optimize power consumption.
• Perform area estimation to meet PPA requirements.
• Develop and maintain automation scripts.

Skills

Proficiency with industry-standard synthesis tools

Strong understanding of static timing analysis

Solid knowledge of Verilog/SystemVerilog

Familiarity with scripting languages

Excellent problem-solving skills

Strong communication and interpersonal skills

Education

Bachelor's or Master's degree in VLSI or Electronics Engineering

Tools

Synopsys DC/FC

Cadence Genus

Synopsys PrimeTime

Cadence Tempus

Synopsys Formality

Cadence Conformal (LEC)

Job description

We are seeking highly motivated Synthesis & Front-End Implementation Engineer to join our dynamic AI NPU team. In this role, you will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.

Job Responsibilities

• Perform logical and physical synthesis of RTL designs for various digital blocks and sub-systems, including hierarchical synthesis methodologies.
• Develop and implement robust timing constraints (SDC) to achieve target frequencies and optimize design performance.
• Conduct STA, identify critical paths, and collaborate with design teams for timing closure.
• Execute formal verification (LEC) to ensure functional equivalency between RTL and synthesized netlists.
• Analyze and optimize power consumption at the front-end stage, utilizing power analysis tools and techniques.
• Perform area estimation and optimization to meet aggressive PPA requirements.
• Collaborate closely with RTL designers, DFT engineers, and physical design engineers to ensure seamless integration and hand-off.
• Develop and maintain automation scripts (Tcl, Python, Perl) for synthesis flows and design analysis.
• Evaluate and integrate new CAD tools and methodologies to improve efficiency and design quality.
• Document design constraints, methodologies, and analysis results thoroughly.

Job Qualifications

• Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field.
• 5+ years of relevant experience in digital ASIC/SoC design, with a focus on synthesis and front-end implementation.
• Proficiency with industry-standard synthesis tools (e.g., Synopsys DC/FC or Cadence Genus).
• Strong experience with physical synthesis and floorplanning aspects is a plus.
• Strong understanding of static timing analysis (STA) concepts and tools (e.g., Synopsys PrimeTime or Cadence Tempus).
• Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal (LEC)).
• Understanding of UPF, low-power design techniques and power analysis concepts.
• Solid knowledge of Verilog/SystemVerilog for digital design.
• Familiarity with scripting languages (Tcl, Python, Perl) for automation.
• Knowledge of DFT (Design for Testability) principles is a plus.
• Excellent problem-solving skills and attention to detail.
• Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment across multiple time zones.