Synthesis Lead Engineer

Mirafra Technologies; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Mirafra Technologies in Bengaluru, India seeks an experienced engineer for placement/power-aware synthesis using Synopsys and Cadence tools. You will work with design and physical teams to define preplacement requirements and timing constraints, ensuring robust reports for floorplanning and timing reviews.

Responsibilities include collaborating across teams to review standard cell profiles, timing models and memory models, and delivering high-quality RTL-to-GDS workflows with strong scripting

Qualifications

• Experience in ASIC design flow and synthesis; familiarity with STA is essential.
• Hands-on experience with logic synthesis and timing analysis.
• Proficiency with Synopsys DC and PT tools and Verilog/VHDL is required.
• Desirable: Perl, TCL and shell scripting.
• Excellent interpersonal and analytical skills with ability to work independently.

Responsibilities

• Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus).
• Work closely with design team to define preplacement requirements & timing constraints.
• Collaborate with physical design team for floorplan, placement & timing reviews.
• Review standard cell profiles, timing models & memory models with cross-functional teams.

Skills

ASIC design flow

Synthesis and STA

Verilog/VHDL

Interpersonal & analytical skills

Perl

TCL

Shell scripting

Tools

Synopsys DC

PT tools

Cadence Genus

Job description

Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus).

Work closely with design team to come up with preplacement requirements & timing constraints.

Work closely with physical design team for floorplan, placement & timing reviews.

Work closely with cross-functional teams to review standard cell profile, timing models & memory models.

Key Skills:

• Good understanding of ASIC design flow.
• Hands on experience in synthesis and static timing analysis.
• Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must.
• Experience in Perl, TCL and shell scripting is desirable.
• Excellent interpersonal & analytical skills with ability to work independently.