Static Timing Analysis (STA)

Tata Consultancy Services; Bengaluru; On-site; INR 1,000,000 - 1,800,000; Full time

Job summary

Tata Consultancy Services in Bengaluru is seeking a Static Timing Analysis (STA) Engineer to develop, validate, and sign off timing constraints for complex ASIC/SoC designs. You will collaborate with RTL, PD, DFT, and Signoff teams to ensure robust timing closure.

The role requires hands-on experience with industry tools and strong understanding of setup/hold, path-based violations, and MCMM analysis across PVT corners.

Qualifications

• Experience with static timing analysis for ASIC/SoC designs
• Strong understanding of setup/hold, capacitance, and path-based violations
• Collaboration with RTL, PD, DFT and Signoff teams

Responsibilities

• Perform static timing analysis using Synopsys PrimeTime or Cadence Tempus
• Develop, validate, and maintain SDC constraints including clocks and exceptions
• Analyze setup/hold, transition, capacitance, and path-based violations
• Support timing closure and ECO implementation with PD teams
• Execute MCMM analysis across PVT corners and modes
• Participate in timing signoff reviews and documentation

Skills

Static timing analysis

SDC constraints

Timing closure

RTL collaboration

Industry tools

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

TCS has always been in the spotlight for being adept in the next big technologies. What we can offer you is a space to explore varied technologies and quench your techie soul.

Role Overview

The Static Timing Analysis (STA) Engineer role focuses on timing constraint development, analysis, closure, and signoff for complex ASIC and SoC designs across multiple technology nodes. The role requires strong STA fundamentals, hands‑on expertise with industry-standard tools, and close collaboration with RTL, Physical Design, DFT, and Signoff teams.

Core Responsibilities (All Levels)

• Perform static timing analysis using Synopsys PrimeTime or Cadence Tempus
• Develop, validate, and maintain SDC constraints including clocks and exceptions
• Analyze setup/hold, transition, capacitance, and path-based violations
• Support timing closure and ECO implementation with PD teams
• Execute MCMM analysis across PVT corners and modes
• Participate in timing signoff reviews and documentation