Tcs Hiring Static Timing Analysis (STA) Engineer For Bangalore

Tata Consultancy Services; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Tata Consultancy Services in Bengaluru is seeking a Senior STA Engineer to own timing constraint development, analysis, closure, and signoff for complex ASIC and SoC designs.

You will collaborate with RTL, Physical Design, DFT, and Signoff teams, perform static timing analysis using industry tools, and contribute to timing reviews and documentation.

Qualifications

• 13+ years of experience in Static Timing Analysis (STA).
• Strong fundamentals in STA concepts and timing closure.

Responsibilities

• Perform static timing analysis using Synopsys PrimeTime or Cadence Tempus
• Develop, validate, and maintain SDC constraints including clocks and exceptions
• Analyze setup/hold, transition, capacitance, and path-based violations
• Support timing closure and ECO implementation with PD teams
• Execute MCMM analysis across PVT corners and modes
• Participate in timing signoff reviews and documentation

Skills

STA fundamentals

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Greetings from TCS!

Job Title: Static Timing Analysis (STA)

Location: Bangalore

Experience Range: 13+ yrs

Job description:

TCS has always been in the spotlight for being adept in the next big technologies. What we can offer you is a space to explore varied technologies and quench your techie soul.

Role Overview

The Static Timing Analysis (STA) Engineer role focuses on timing constraint development, analysis, closure, and signoff for complex ASIC and SoC designs across multiple technology nodes. The role requires strong STA fundamentals, hands-on expertise with industry-standard tools, and close collaboration with RTL, Physical Design, DFT, and Signoff teams.

Core Responsibilities (All Levels)

• Perform static timing analysis using Synopsys PrimeTime or Cadence Tempus
• Develop, validate, and maintain SDC constraints including clocks and exceptions
• Analyze setup/hold, transition, capacitance, and path-based violations
• Support timing closure and ECO implementation with PD teams
• Execute MCMM analysis across PVT corners and modes
• Participate in timing signoff reviews and documentation