Standardcell Layout Engineer

Exiger Technologies; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Exiger Technologies is seeking an IC layout engineer for Bengaluru with strong knowledge of standard cell layout design and CMOS logic. Experience in Std cell Layout for Bulk CMOS is required; FINFET is welcome but not mandatory. Proficiency with Cadence Virtuoso and Calibre is essential, plus ability to debug layout issues and work well in a team.

Candidate should be a good team player and comfortable with scripting in SKILL or related languages. On-site role based in Bengaluru.

Qualifications

• Knowledge of standard cell layout design and CMOS logic.
• Experience in Std cell Layout for Bulk CMOS; FINFET experience preferred but not required.
• Proficiency with Cadence Virtuoso and Calibre.
• Experience in ESD layouts, antenna/EM handling.
• Ability to independently debug layout issues.
• Good team player with collaborative mindset.
• Familiarity with SKILL or other scripting languages.

Skills

Standard cell layout design

CMOS logic

Debug layout issues

Team work

Scripting

Tools

Cadence Virtuoso

Calibre

Job description

Requirements

• Good knowledge of Standard cell layout design
• Good knowledge of CMOS logic
• Experience in working on Std cell Layout for Bulk CMOS. FINFET experience is not a must but preferable.
• Expertise in using industry-standard tools like cadence Virtuoso, Calibre
• Experience in implementation of ESD layouts, handling Antenna/EM, etc
• Ability to independently debug layout issues
• Good team player
• Good in SKILL programming or other scripting languages