Staff Physical Design Engineer

Silicon Labs GmbH; Hyderabad; On-site; INR 4,400,000 - 6,800,000; Full time

Benefits offered by this job

Equity RSUs

ESPP

Insurance

NPS

Flexible work

Childcare

Job summary

Silicon Labs in Hyderabad is seeking a highly skilled Physical Design engineer to join its Silicon Engineering team to drive the design, implementation, and optimization of advanced SoCs using state-of-the-art methodologies.

You will lead synthesis, floorplanning, place-and-route, timing closure and sign-off flows, mentor juniors, and collaborate with RTL, DFT, verification, and packaging teams to deliver world-class silicon.

Qualifications

• 8+ years of ASIC physical design experience.
• Strong hands-on with rtl-to-gdsII flow and sign-off.
• Exposure to UPF/CPF and low-power techniques.
• Excellent leadership and communication skills.

Responsibilities

• Lead end-to-end physical design flow for complex SoCs and IP blocks.
• Define floorplanning, CTS, placement, routing, and timing closure strategies.
• Own and optimize PPA metrics for assigned designs.
• Manage constraints, synthesis approaches, and sign-off (timing, IR drop).
• Collaborate with RTL, DFT, verification, and packaging teams; mentor juniors.

Skills

Synthesis

Floorplanning

Place-and-Route

Timing Closure

Low-Power Design

Mentoring

Education

B.E./B.Tech or M.E./M.Tech in Electrical Engineering, VLSI

Tools

Synopsys ICC2

Fusion Compiler

PrimeTime

Cadence Innovus

Tempus

Job description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Meet the Team

Join a dynamic Physical Design team that drives end-to-end SoC implementation, from RTL to tape-out. We work closely with design, verification, and architecture groups to deliver high-performance, low-power solutions. Collaboration, innovation, and technical excellence define our culture—making this an exciting place to grow, lead, and make a real impact.

About the Role

We are seeking a highly skilled Physical Design to join our Silicon Engineering team in Hyderabad. In this role, you will drive the design, implementation, and optimization of advanced SoCs using state-of-the-art physical design methodologies. You will work on challenging synthesis, floorplanning, place-and-route, timing closure, and sign-off flows while mentoring a team of engineers and collaborating with cross-functional groups. This is an excellent opportunity to contribute to world-class silicon solutions and grow as a technical leader.

Responsibilities

• Lead and execute the end-to-end physical design flow for complex SoCs and IP blocks (RTL handoff to GDSII).
• Define and drive strategies for floorplanning, CTS, placement, routing, and timing closure.
• Own and optimize PPA (Power, Performance, Area) metrics for assigned designs.
• Manage design constraints, synthesis strategies, and sign-off (timing, IR drop, EM, DRC/LVS).
• Collaborate with RTL, DFT, verification, and packaging teams for seamless integration.
• Drive EDA tool automation and methodology improvements for efficiency and scalability.
• Mentor and guide junior engineers to foster technical growth and excellence.
• Work with foundries and vendors on process bring-up, PDK updates, and tape-out readiness.

Requirements

• B.E./B.Tech or M.E./M.Tech in Electrical Engineering, VLSI, or related field.
• 8+ years of experience in ASIC physical design
• Strong hands-on expertise in Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus, Tempus), or similar tools.
• Proven background in timing analysis, low-power methodologies, and ECO flows.
• Deep understanding of the architecture-to-GDSII flow and sign-off requirements.
• Excellent problem-solving, leadership, and communication skills.
• Preferred Qualification: Experience in chip-level integration and hierarchical design methodologies.
• Knowledge of UPF/CPF, power gating, DVFS, and other low-power techniques.
• Familiarity with DFT, STA, and physical verification methodologies.
• Exposure to multi-clock, multi-voltage, and multi-domain designs.
• Previous experience with customer-facing or cross-site collaboration.

Benefits & Perks

• Equity Rewards (RSUs)
• Employee Stock Purchase Plan (ESPP)
• Insurance plans with Outpatient cover
• National Pension Scheme (NPS)
• Flexible work policy
• Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

By offering challenging projects, technical mentorship, and continuous learning opportunities, we ensure our employees thrive at every stage of their careers. Here, you’ll work alongside some of the industry’s brightest minds, tackling complex problems that deepen your expertise and expand your horizons. Whether you’re building new skills or shaping your career path, we’re dedicated to supporting your growth and celebrating your success every step of the way.

Please note that our Company never asks for personal information unrelated to the job application process, such as bank or credit card data and never charges any fees to apply to any jobs.

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