Manager / Senior Manager – Design Verification

Silicon Labs GmbH; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Equity RSUs

Insurance (Outpatient)

National Pension Scheme

Flexible work policy

Childcare support

Job summary

Silicon Labs in Hyderabad is seeking an experienced Manager/Senior Manager – Design Verification to lead a high-performing verification team across IP and SoC projects. You will drive verification planning, execution, and on-time delivery while providing strong technical and people leadership.

You will collaborate with global teams, advance verification methodologies, automation, and AI-assisted workflows, and mentor engineers to build a culture of excellence and continuous learning.

Qualifications

• B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Computer Engineering, VLSI, or a related field.
• 10–15 years of experience in Design Verification, with strong expertise in IP, subsystem, and SoC verification.
• Proven experience leading and developing Design Verification teams in a multi-site development environment.
• Strong hands-on expertise in SystemVerilog, UVM, assertions, constrained-random verification, functional coverage, and regression management.
• Demonstrated success in delivering multiple complex verification projects from planning through sign-off.
• Strong understanding of verification planning, testbench architecture, coverage closure, debug methodologies, and verification metrics.
• Experience driving verification methodology, automation, reuse, and productivity improvements across teams.
• Excellent leadership, problem-solving, communication, stakeholder management, and cross-functional collaboration skills.

Responsibilities

• Lead and develop a high-performing Design Verification team responsible for IP and SoC verification across multiple projects.
• Drive verification planning, execution, functional coverage closure, regression management, sign-off, and on-time delivery with high quality.
• Provide technical leadership in SystemVerilog, UVM, assertions, constrained-random verification, coverage-driven verification, and debug methodologies.
• Manage project priorities, technical risks, resource allocation, and dependencies across multiple programs.
• Collaborate with Design, Architecture, Firmware, Validation, and Program Management teams across global sites.
• Define and drive verification strategies for complex IPs, subsystems, and SoCs.
• Drive continuous improvements in verification methodologies, automation, regression efficiency, and reusable verification infrastructure.
• Champion innovation through the adoption of new verification techniques, tools, formal methods, AI-assisted workflows, and industry best practices.
• Mentor engineers, develop technical leaders, and build a culture of engineering excellence, accountability, collaboration, and continuous learning.
• Establish clear execution metrics, monitor project progress, identify risks early, and drive issues to closure.
• Support hiring, performance management, career development, and organizational capability building for the verification team.

Skills

SystemVerilog

UVM

Assertions

Constrained random

Functional coverage

Regression management

Leadership

Cross-functional collaboration

Education

BE/B.Tech or ME/M.Tech in Electrical/ Computer Engineering / VLSI

Tools

AI-assisted tools

Python

Tcl

Emulation

Formal verification

Job description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting‑edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Meet the Team

Join a dynamic Design Verification team responsible for delivering robust IP and SoC solutions across multiple product programs. We work closely with Design, Architecture, Firmware, Validation, and Program Management teams across global locations to ensure high‑quality silicon delivery. Collaboration, innovation, technical excellence, and continuous improvement define our culture, making this an exciting opportunity to lead, grow, and make a significant impact.

About the Role

We are seeking an experienced Manager / Senior Manager – Design Verification to join our Silicon Engineering team in Hyderabad. In this role, you will lead and develop a high-performing verification team responsible for IP and SoC verification across multiple projects. You will drive verification planning, execution, closure, and on‑time delivery while providing strong technical and people leadership. You will also collaborate with cross‑functional and global teams, improve verification methodologies and automation, and champion the adoption of advanced verification techniques, AI‑assisted workflows, and industry best practices. This is an excellent opportunity to lead complex verification programs, build scalable verification capabilities, and develop the next generation of engineering leaders.

Responsibilities

• Lead and develop a high-performing Design Verification team responsible for IP and SoC verification across multiple projects.
• Drive verification planning, execution, functional coverage closure, regression management, sign‑off, and on‑time delivery with high quality.
• Provide technical leadership in SystemVerilog, UVM, assertions, constrained‑random verification, coverage‑driven verification, and debug methodologies.
• Manage project priorities, technical risks, resource allocation, and dependencies across multiple programs.
• Collaborate with Design, Architecture, Firmware, Validation, and Program Management teams across global sites.
• Define and drive verification strategies for complex IPs, subsystems, and SoCs.
• Drive continuous improvements in verification methodologies, automation, regression efficiency, and reusable verification infrastructure.
• Champion innovation through the adoption of new verification techniques, tools, formal methods, AI‑assisted workflows, and industry best practices.
• Mentor engineers, develop technical leaders, and build a culture of engineering excellence, accountability, collaboration, and continuous learning.
• Establish clear execution metrics, monitor project progress, identify risks early, and drive issues to closure.
• Support hiring, performance management, career development, and organizational capability building for the verification team.

Requirements

• B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Computer Engineering, VLSI, or a related field.
• 10–15 years of experience in Design Verification, with strong expertise in IP, subsystem, and SoC verification.
• Proven experience leading and developing Design Verification teams in a multi‑site development environment.
• Strong hands‑on expertise in SystemVerilog, UVM, assertions, constrained‑random verification, functional coverage, and regression management.
• Demonstrated success in delivering multiple complex verification projects from planning through sign‑off.
• Strong understanding of verification planning, testbench architecture, coverage closure, debug methodologies, and verification metrics.
• Experience driving verification methodology, automation, reuse, and productivity improvements across teams.
• Excellent leadership, problem‑solving, communication, stakeholder management, and cross‑functional collaboration skills.

Preferred Qualifications

• Experience leading verification for complex SoCs, subsystems, processors, connectivity, mixed‑signal, or low‑power designs.
• Experience with formal verification, emulation, FPGA prototyping, performance verification, or hardware‑software co‑verification.
• Knowledge of low‑power verification methodologies, including UPF‑based verification and multi‑power‑domain designs.
• Experience developing reusable UVM environments, verification IP, automation frameworks, and scalable regression infrastructure.
• Exposure to AI‑assisted verification, data analytics, advanced debug tools, or scripting languages such as Python, Perl, or Tcl.
• Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision‑making.

Benefits & Perks

Not only will you be joining a highly skilled and tight‑knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees.

Employment decisions are made on the basis of qualifications and job‑related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

At Silicon Labs, we hire and empower great talent to achieve their full potential. By offering challenging projects, technical mentorship, and continuous learning opportunities, we ensure our employees thrive at every stage of their careers. Here, you’ll work alongside some of the industry’s brightest minds, tackling complex problems that deepen your expertise and expand your horizons. Whether you’re building new skills or shaping your career path, we’re dedicated to supporting your growth and celebrating your success every step of the way.

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