Staff Engineer - IC Design

Silicon Labs; Hyderabad; On-site; INR 2,400,000 - 4,200,000; Full time

Benefits offered by this job

Equity Rewards (RSUs)

Employee Stock Purchase Plan (ESPP)

Insurance plans with Outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs in Hyderabad seeks an experienced RTL Design Engineer with 5–15 years of hands-on digital design and IP development. You will design synthesizable RTL in Verilog/SystemVerilog for SoC IP blocks and drive IP development from spec to tape-out, ensuring competitive performance, power, and area.

Exposure to wireless subsystems, such as Wi‑Fi, and familiarity with AMBA protocols, Synthesis, timing analysis, and EDA tools will help you succeed.

Qualifications

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field.
• 5–15 years of experience in RTL design and digital IP development.
• Strong proficiency in Verilog/SystemVerilog and RTL design fundamentals.
• Familiarity with FSMs, datapath design, pipelining, and clock-domain crossing concepts.
• Experience with synthesis, timing analysis, and RTL/gate-level debugging.

Responsibilities

• Develop high-quality, synthesizable RTL (Verilog/SystemVerilog) for digital IP blocks.
• Drive IP development from specification to tape-out.
• Ensure designs meet performance, power, and area (PPA) targets.
• Develop and maintain design documentation (micro-architecture spec, design spec, integration guide).
• Collaborate with verification teams to develop test plans and debug functional issues.
• Support synthesis, lint, CDC/RDC, and timing closure activities.
• Work closely with SoC integration teams for IP integration and bring-up.
• Support post-silicon validation and debug.
• Contribute to IP reuse, configurability, and design methodology improvements.
• Mentor junior engineers

Skills

Verilog/SystemVerilog

RTL design

Digital IP development

AMBA protocols

Synthesis & timing analysis

CDC/RDC

Low-power design concepts

EDA tools (Synopsys/Cadence/Mentor)

Wireless IP awareness

Education

Bachelor's or Master's degree in Electronics/Electrical Engineering

Tools

Synopsys

Cadence

Mentor

Job description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Role Overview

We are seeking an experienced RTL Design Engineer with 5–15 years of hands-on experience in digital design and IP development. The ideal candidate will have strong expertise in RTL architecture and micro-architecture definition, with experience developing reusable IP for SoC integration.

Exposure to wireless systems (preferably Wi-Fi) and communication/peripheral IP such as SPI, UART, I2C, DMA, etc., is highly desirable.

Key Responsibilities

• Develop high-quality, synthesizable RTL (Verilog/SystemVerilog) for digital IP blocks.
• Drive IP development from specification to tape-out.
• Ensure designs meet performance, power, and area (PPA) targets.
• Develop and maintain design documentation (micro-architecture spec, design spec, integration guide).
• Collaborate with verification teams to develop test plans and debug functional issues.
• Support synthesis, lint, CDC/RDC, and timing closure activities.
• Work closely with SoC integration teams for IP integration and bring-up.
• Support post-silicon validation and debug.
• Contribute to IP reuse, configurability, and design methodology improvements.
• Mentor junior engineers

Required Qualifications

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field.
• 5–15 years of experience in RTL design and digital IP development.
• Strong proficiency in Verilog/SystemVerilog.
• Solid understanding of:
  • Digital design fundamentals
  • FSM and datapath design
  • Pipelining and performance optimization
  • Clock domain crossing (CDC) and reset domain crossing (RDC)
  • Low-power design concepts
• Experience with synthesis and timing analysis.
• Strong RTL and gate-level debugging skills.
• Familiarity with industry-standard EDA tools (Synopsys/Cadence/Mentor).
• Experience with AMBA protocols (AXI/AHB/APB).

Preferred Experience

• Experience developing communication or peripheral IP such as:
  • SPI, UART, I2C/I3C
  • DMA controllers
  • Timers, interrupt controllers
  • Memory controllers
• Exposure to wireless subsystems, preferably Wi-Fi (IEEE 802.11) architecture or MAC-level understanding.
• Experience with packet processing or high-speed data path design.
• Exposure to security/crypto IP is a plus.
• Scripting knowledge (Python/Perl/TCL).
• Experience in advanced technology nodes is an advantage.

"Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making"

Benefits & Perks

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Equity Rewards (RSUs)
• Employee Stock Purchase Plan (ESPP)
• Insurance plans with Outpatient cover
• National Pension Scheme (NPS)
• Flexible work policy
• Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.