Lead Engineer – IC Design (STA Lead )

Silicon Labs GmbH; Hyderabad; On-site; INR 3,500,000 - 7,000,000; Full time

Benefits offered by this job

Equity Rewards (RSUs)

Insurance plans with Outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs, located in Hyderabad, seeks a highly skilled Lead Design Engineer to join our Silicon Engineering Team. This role leads and participates in BE implementation, including constraints management, synthesis, and STA to ensure timing closure for high-performance SoCs and ASICs.

You will collaborate with cross-functional teams to deliver timing sign-off, low power optimization, and PPA improvements while mentoring junior engineers across the BE cycle from RTL to GDSII.

Qualifications

• 7+ years of experience in ASIC physical design.
• Strong background in synthesis, constraints, margins and timing analysis/fixing.
• Excellent problem-solving and communication skills.

Responsibilities

• Hands-on development, management and validation of timing constraints for RTL-to-GDSII flow in collaboration with Design & DFT teams
• Own STA execution for digital blocks and top-level designs
• Help in CTS spec generation in collaboration with Design & PnR engineers
• Run Logical Equivalence checks using industry standard tools
• Develop low power and UPF development & lowe power checks
• Generate and interpret timing reports using industry-standard tools
• Implement timing ECOs to resolve critical path issues
• Contribute to timing methodology improvements and automation
• Perform timing checks for CDC, false paths, and multicycle paths
• Lead the team and execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII)
• Own and optimize power, performance, and area (PPA) metrics for assigned designs
• Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR drop, EM, DRC/LVS)
• Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure seamless integration
• Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability
• Mentor and guide junior engineers, fostering technical growth and design excellence

Skills

ASIC PD experience

Timing analysis

Problem solving

Communication skills

Automation scripting

Education

Bachelor’s or Master’s in ECE/EEE/VLSI

Tools

Cadence Genus

Cadence Innovus

Cadence Tempus

Synopsys ICC2

Fusion Compiler

PrimeTime

Job description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. Meet the team: We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance.

About the role

We are seeking a highly skilled Lead Design Engineer to join our Silicon Engineering Team in Hyderabad. This role involves leading and hands on various stages of BE implementation flow including, but not limited to, Constraints management, Synthesis and Static Timing Analysis (STA). You will be responsible for constraints development, timing sign-off of high-performance SoCs and ASICs. You’ll work closely with cross-functional teams to ensure timing closure across various operating modes and process corners. Ideal candidate will have exposure to full gamut of BE cycle – synthesis, Place & route, Logic equivalence, UPF & low power checks, STA & PV Signoff and should aspire & be able to grow as BE lead taking care of full BE implementation cycle of our cutting-edge SoCs through advanced physical design methodologies. PPA optimization and Low power implementation methodologies exposure is a must.

Responsibilities

• Hands-on development, management and validation of timing constraints for RTL-to-GDSII flow in collaboration with Design & DFT teams
• Own STA execution for digital blocks and top-level designs
• Help in CTS spec generation in collaboration with Design & PnR engineers
• Run Logical Equivalence checks using industry standard tools
• Develop low power and UPF development & lowe power checks
• Generate and interpret timing reports using industry-standard tools
• Implement timing ECOs to resolve critical path issues
• Contribute to timing methodology improvements and automation
• Perform timing checks for CDC, false paths, and multicycle paths
• Lead the team and execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII)
• Own and optimize power, performance, and area (PPA) metrics for assigned designs
• Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR drop, EM, DRC/LVS)
• Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure seamless integration
• Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability
• Mentor and guide junior engineers, fostering technical growth and design excellence

Requirements

• Bachelor’s or Master’s degree in ECE, EEE, VLSI or related field
• 7+ years of experience in ASIC physical design
• Hands-on expertise in Industry standard EDA tools: Cadence (Genus, Innovus, Tempus, LEC, CLP), or equivalent or Synopsys (ICC2, Fusion Compiler, PrimeTime)
• Strong background in synthesis, constraints, margins and timing analysis/fixing
• Solid understanding of architecture-to-GDSII flows and sign-off requirements
• Excellent problem-solving and communication skills

Preferred Qualifications

• Experience with chip-level integration and hierarchical design methodologies
• Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS)
• Familiarity with DFT, Floor planning, PnR, and physical verification/IR analysis
• Exposure to multi-clock, multi-voltage, and multi-domain designs
• Experience of leading small (4-10 members) teams in related domain
• Automation expertise using perl/tcl/tk/python
• Exposure to multi site environment and collaboration

Benefits & Perks

• Equity Rewards (RSUs)
• Insurance plans with Outpatient cover
• National Pension Scheme (NPS)
• Flexible work policy
• Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

At Silicon Labs, we hire and empower great talent to achieve their full potential. By offering challenging projects, technical mentorship, and continuous learning opportunities, we ensure our employees thrive at every stage of their careers. Here, you’ll work alongside some of the industry’s brightest minds, tackling complex problems that deepen your expertise and expand your horizons. Whether you’re building new skills or shaping your career path, we’re dedicated to supporting your growth and celebrating your success every step of the way.