Lead RTL Design Engineer

ACL Digital; Chennai; On-site; INR 900,000 - 1,500,000; Full time

Job summary

ACL Digital is looking for an experienced RTL Design Engineer in Chennai, India, with 6 to 9 years of expertise in RTL design, constraints, and interface timing challenges. The ideal candidate should have a strong domain knowledge in timing analysis along with coding experience in Verilog, VHDL, and System Verilog. Key responsibilities include collaborative performance management and proactive interaction with verification teams. Familiarity with scripting and power management strategies is highly preferred.

Qualifications

• 6 to 9 years of experience in RTL design and implementation.
• Strong domain knowledge in timing analysis and synthesis.
• Experience in micro-architecture design for cores and ASICs.

Responsibilities

• Collaborate with cross-functional teams to manage performance and power constraints.
• Debug and solve issues independently.
• Interact with verification engineers proactively.

Skills

RTL Design

Verilog

VHDL

System Verilog

Power Management

Scripting (Pearl/Python/TCL)

Job description

6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.

• Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.
• Experience with RTL coding using Verilog/VHDL/System Verilog.
• Experience in micro-architecture & designing cores and ASICs.
• Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc.
• Exposure in scripting (Pearl/Python/TCL).
• Collaborate closely with cross-function team to research, design and implement performance, constraints and power management strategy for product roadmap.
• Good team player. Need to interact with the other teams/verification engineers proactively.
• Ability to debug and solve issues independently.